Compensation technique for nonlinear distortion in RF circuits for multi-standard wireless systems

Recent technological advances in the RF and wireless industry has led to the design requirement of more sophisticated devices which can meet stringent specifications of bandwidth, data rate and throughput. These devices are required to be extremely sensitive and hence any external interference from other systems can severely affect the device and the output. This thesis introduces the existing problem in nonlinear components in a multi-standard wireless system due to interfering signals and suggests potential solution to the problem. Advances in RF and wireless systems with emerging new communication standards have made reconfigurablility and tunability a very viable option. RF transceivers are optimised for multi-standard operation, where one band of frequency can act as an interfering signal to the other band. Due to the presence of nonlinear circuits in the transceiver chains such as power amplifiers, reconfigurable and tunable filters and modulators, these interfering signals produce nonlinear distortion products which can deform the output signal considerably. Hence it becomes necessary to block these interfering signals using special components. The main objective of this thesis is to analyse and experimentally verify the nonlinear distortions in various RF circuits such as reconfigurable and tunable filters and devise ways to minimize the overall nonlinear distortion in the presence of other interfering signals. Reconfigurbality and tunablity in filters can be achieved using components such as varactor diodes, PIN diodes and optical switches. Nonlinear distortions in such components are measured using different signals and results noted. The compensation method developed to minimize nonlinear distortions in RF circuits caused due to interfering signals is explored thoroughly in this thesis. Compensation method used involves the design of novel microstrip bandstop filters which can block the interfering signals and hence give a clean output spectrum at the final stage. Recent years have seen the emergence of electronic band gap technology which has “band gap” properties meaning that a bandstop response is seen within particular range of frequency. This concept was utilised in the design of several novel bandstop filters using defected microstrip structure. Novel tunable bandstop filters has been introduced in order to block the unwanted signal. Fixed single-band and dual-band filters using DMS were fabricated with excellent achieved results. These filters were further extended to tunable structures. A dual-band tunable filter with miniaturized size was developed and designed. The designed filters were further used in the compensation technique where different scenarios showing the effect of interfering signals in wireless transceiver were described. Mathematical analysis proved the validation of the use of a bandstop filter as an inter-stage component. Distortion improvements of around 10dB have been experimentally verified using a power amplifier as device under test. Further experimental verification was carried out with a transmitter which included reconfigurable RF filters and power amplifier where an improvement of 15dB was achieved

NASA. Lewis Research Center Advanced Modulation and Coding Project: Introduction and overview

The Advanced Modulation and Coding Project at LeRC is sponsored by the Office of Space Science and Applications, Communications Division, Code EC, at NASA Headquarters and conducted by the Digital Systems Technology Branch of the Space Electronics Division. Advanced Modulation and Coding is one of three focused technology development projects within the branch's overall Processing and Switching Program. The program consists of industry contracts for developing proof-of-concept (POC) and demonstration model hardware, university grants for analyzing advanced techniques, and in-house integration and testing of performance verification and systems evaluation. The Advanced Modulation and Coding Project is broken into five elements: (1) bandwidth- and power-efficient modems; (2) high-speed codecs; (3) digital modems; (4) multichannel demodulators; and (5) very high-data-rate modems. At least one contract and one grant were awarded for each element

An Overview on Application of Machine Learning Techniques in Optical Networks

Today's telecommunication networks have become sources of enormous amounts of widely heterogeneous data. This information can be retrieved from network traffic traces, network alarms, signal quality indicators, users' behavioral data, etc. Advanced mathematical tools are required to extract meaningful information from these data and take decisions pertaining to the proper functioning of the networks from the network-generated data. Among these mathematical tools, Machine Learning (ML) is regarded as one of the most promising methodological approaches to perform network-data analysis and enable automated network self-configuration and fault management. The adoption of ML techniques in the field of optical communication networks is motivated by the unprecedented growth of network complexity faced by optical networks in the last few years. Such complexity increase is due to the introduction of a huge number of adjustable and interdependent system parameters (e.g., routing configurations, modulation format, symbol rate, coding schemes, etc.) that are enabled by the usage of coherent transmission/reception technologies, advanced digital signal processing and compensation of nonlinear effects in optical fiber propagation. In this paper we provide an overview of the application of ML to optical communications and networking. We classify and survey relevant literature dealing with the topic, and we also provide an introductory tutorial on ML for researchers and practitioners interested in this field. Although a good number of research papers have recently appeared, the application of ML to optical networks is still in its infancy: to stimulate further work in this area, we conclude the paper proposing new possible research directions

Algorithm-Architecture Co-Design for Digital Front-Ends in Mobile Receivers

The methodology behind this work has been to use the concept of algorithm-hardware co-design to achieve efficient solutions related to the digital front-end in mobile receivers. It has been shown that, by looking at algorithms and hardware architectures together, more efficient solutions can be found; i.e., efficient with respect to some design measure. In this thesis the main focus have been placed on two such parameters; first reduced complexity algorithms to lower energy consumptions at limited performance degradation, secondly to handle the increasing number of wireless standards that preferably should run on the same hardware platform. To be able to perform this task it is crucial to understand both sides of the table, i.e., both algorithms and concepts for wireless communication as well as the implications arising on the hardware architecture. It is easier to handle the high complexity by separating those disciplines in a way of layered abstraction. However, this representation is imperfect, since many interconnected "details" belonging to different layers are lost in the attempt of handling the complexity. This results in poor implementations and the design of mobile terminals is no exception. Wireless communication standards are often designed based on mathematical algorithms with theoretical boundaries, with few considerations to actual implementation constraints such as, energy consumption, silicon area, etc. This thesis does not try to remove the layer abstraction model, given its undeniable advantages, but rather uses those cross-layer "details" that went missing during the abstraction. This is done in three manners: In the first part, the cross-layer optimization is carried out from the algorithm perspective. Important circuit design parameters, such as quantization are taken into consideration when designing the algorithm for OFDM symbol timing, CFO, and SNR estimation with a single bit, namely, the Sign-Bit. Proof-of-concept circuits were fabricated and showed high potential for low-end receivers. In the second part, the cross-layer optimization is accomplished from the opposite side, i.e., the hardware-architectural side. A SDR architecture is known for its flexibility and scalability over many applications. In this work a filtering application is mapped into software instructions in the SDR architecture in order to make filtering-specific modules redundant, and thus, save silicon area. In the third and last part, the optimization is done from an intermediate point within the algorithm-architecture spectrum. Here, a heterogeneous architecture with a combination of highly efficient and highly flexible modules is used to accomplish initial synchronization in at least two concurrent OFDM standards. A demonstrator was build capable of performing synchronization in any two standards, including LTE, WiFi, and DVB-H

LTE implementation on CGRA based SiLago Platform

Abstract. This thesis implements long term evolution (LTE) transmission layer on a coarse grained reconfigurable called, dynamically reconfigurable resource array (DRRA). Specifically, we implement physical downlink shared channel baseband signal processing blocks (PDSCH) at high level. The overall implementation follows silicon large grain object (SiLago) design methodology. The methodology employs SiLago blocks instead of mainstream standard cells. The main ambition of this thesis was to prove that a standard as complex as LTE can be implemented using the in-house SiLago framework. The work aims to prove that customized design with efficiency close to application specific integrated circuit (ASIC) for LTE can be generated with the programming ease of MATLAB. During this thesis, we have generated a completely parametrizable LTE standard at high level