A Stochastic Conjugate Gradient Method for Approximation of Functions

A stochastic conjugate gradient method for approximation of a function is proposed. The proposed method avoids computing and storing the covariance matrix in the normal equations for the least squares solution. In addition, the method performs the conjugate gradient steps by using an inner product that is based stochastic sampling. Theoretical analysis shows that the method is convergent in probability. The method has applications in such fields as predistortion for the linearization of power amplifiers.Comment: 21 pages, 5 figure

Contribution to dimensionality reduction of digital predistorter behavioral models for RF power amplifier linearization

The power efficiency and linearity of radio frequency (RF) power amplifiers (PAs) are critical in wireless communication systems. The main scope of PA designers is to build the RF PAs capable to maintain high efficiency and linearity figures simultaneously. However, these figures are inherently conflicted to each other and system-level solutions based on linearization techniques are required. Digital predistortion (DPD) linearization has become the most widely used solution to mitigate the efficiency versus linearity trade-off. The dimensionality of the DPD model depends on the complexity of the system. It increases significantly in high efficient amplification architectures when considering current wideband and spectrally efficient technologies. Overparametrization may lead to an ill-conditioned least squares (LS) estimation of the DPD coefficients, which is usually solved by employing regularization techniques. However, in order to both reduce the computational complexity and avoid ill-conditioning problems derived from overparametrization, several efforts have been dedicated to investigate dimensionality reduction techniques to reduce the order of the DPD model. This dissertation contributes to the dimensionality reduction of DPD linearizers for RF PAs with emphasis on the identification and adaptation subsystem. In particular, several dynamic model order reduction approaches based on feature extraction techniques are proposed. Thus, the minimum number of relevant DPD coefficients are dynamically selected and estimated in the DPD adaptation subsystem. The number of DPD coefficients is reduced, ensuring a well-conditioned LS estimation while demanding minimum hardware resources. The presented dynamic linearization approaches are evaluated and compared through experimental validation with an envelope tracking PA and a class-J PA The experimental results show similar linearization performance than the conventional LS solution but at lower computational cost.La eficiencia energetica y la linealidad de los amplificadores de potencia (PA) de radiofrecuencia (RF) son fundamentales en los sistemas de comunicacion inalambrica. El principal objetivo a alcanzar en el diserio de amplificadores de radiofrecuencia es lograr simultaneamente elevadas cifras de eficiencia y de linealidad. Sin embargo, estas cifras estan inherentemente en conflicto entre si, y se requieren soluciones a nivel de sistema basadas en tecnicas de linealizacion. La linealizacion mediante predistorsion digital (DPD) se ha convertido en la solucion mas utilizada para mitigar el compromise entre eficiencia y linealidad. La dimension del modelo del predistorsionador DPD depende de la complejidad del sistema, y aumenta significativamente en las arquitecturas de amplificacion de alta eficiencia cuando se consideran los actuales anchos de banda y las tecnologfas espectralmente eficientes. El exceso de parametrizacion puede conducir a una estimacion de los coeficientes DPD, mediante minimos cuadrados (LS), mal condicionada, lo cual generalmente se resuelve empleando tecnicas de regularizacion. Sin embargo, con el fin de reducir la complejidad computacional y evitar dichos problemas de mal acondicionamiento derivados de la sobreparametrizacion, se han dedicado varies esfuerzos para investigar tecnicas de reduccion de dimensionalidad que permitan reducir el orden del modelo del DPD. Esta tesis doctoral contribuye a aportar soluciones para la reduccion de la dimension de los linealizadores DPD para RF PA, centrandose en el subsistema de identificacion y adaptacion. En concrete, se proponen varies enfoques de reduccion de orden del modelo dinamico, basados en tecnicas de extraccion de caracteristicas. El numero minimo de coeficientes DPD relevantes se seleccionan y estiman dinamicamente en el subsistema de adaptacion del DPD, y de este modo la cantidad de coeficientes DPD se reduce, lo cual ademas garantiza una estimacion de LS bien condicionada al tiempo que exige menos recursos de hardware. Las propuestas de linealizacion dinamica presentados en esta tesis se evaluan y comparan mediante validacion experimental con un PA de seguimiento de envolvente y un PA tipo clase J. Los resultados experimentales muestran unos resultados de linealizacion de los PA similares a los obtenidos cuando se em plea la solucion LS convencional, pero con un coste computacional mas reducido.Postprint (published version

Multiple lookup table predistortion for adaptive modulation

This paper presents a multiple LUT digital adaptive predistorter based on a Hammerstein model that uses the return channel to feed back information from the receiver, concretely the bit error rate (BER), in order to train and later adapt the specific LUT gains that permit always operating at the best back-off level. This new predistorter architecture is aimed at coping with modern communication standards that use adaptive modulation (such as IEEE 802.11 or IEEE 802.16) and therefore continuously searching the best linear amplification to maximize power efficiency at the time that a certain quality of service (BER) in reception is guaranteed. Simulations provided will show the advantages of this multi-LUT configuration, where in front of different channel conditions, linear and efficient amplification (minimum back-off) is achieved at the time that a certain level of BER at reception is ensured. Index terms – Lookup tables (LUT), digital adaptive predistortion, Hammerstein models, adaptive modulation systems, peak to average power ratio (PAPR), bit error rate (BER).Peer Reviewe

Digital Predistortion of Power Amplifiers for Wireless Applications

Digital predistortion is one of the most cost effective ways among all linearization techniques. However, most of the existing designs treat the power amplifier as a memoryless device. For wideband or high power applications, the power amplifier exhibits memory effects, for which memoryless predistorters can achieve only limited linearization performance. In this dissertation, we propose novel predistorters and their parameter extraction algorithms. We investigate a Hammerstein predistorter, a memory polynomial predistorter, and a new combined model based predistorter. The Hammerstein predistorter is designed specifically for power amplifiers that can be modeled as a Wiener system. The memory polynomial predistorter can correct both the nonlinear distortions and the linear frequency response that may exist in the power amplifier. Real-time implementation aspects of the memory polynomial predistorter are also investigated. The new combined model includes the memory polynomial model and the Murray Hill model, thus extending the predistorter's ability to compensate for strong memory effects in the power amplifier. The predistorter models considered in this dissertation include both even- and odd-order nonlinear terms. By including these even-order nonlinear terms, we have a richer basis set, which offers appreciable improvement. In reality, however, the performance of a predistortion system can also be affected by the analog imperfections in the transmitter, which are introduced by the analog components; mostly analog filters and quadrature modulators. There are two common configurations for the upconversion chain in the transmitter: two-stage upconversion and direct upconversion. For a two-stage upconversion transmitter, we design a band-limited equalizer to compensate for the frequency response of the surface acoustic wave (SAW) filter which is usually employed in the IF stage. For a direct upconversion transmitter, we develop a model to describe the frequency-dependent gain/phase imbalance and dc offset. We then develop two methods to construct compensators for the imbalance and dc offset. These compensation techniques help to correct for the analog imperfections, which in turn improve the overall predistortion performance.Ph.D.Committee Chair: G. Tong Zhou; Committee Member: J. Stevenson Kenney; Committee Member: Jianmin Qu; Committee Member: W. Marshall Leach; Committee Member: Ye (Geoffrey) L

Modelação comportamental e pré-distorção digital de transmissores de rádio-frequência

Doutoramento em Engenharia ElectrotécnicaNos atuais sistemas de telecomunicações, os transmissores de rádio-frequência são desenvolvidos tendo maioritariamente em conta a eficiência da conversão da potência fornecida da fonte em potência de rádio-frequência. Este tipo de desenho resulta em amplificadores de potência com características de transmissão não-lineares, que distorcem severamente o envelope de informação no processo de amplificação, gerando distorção fora da banda. Para corrigir este problema utiliza-se um processo de compensação não linear, sendo que a pré-distorção digital se tem favorecido pela sua flexibilidade e precisão. Este método é tipicamente aplicado de uma forma cega, por força bruta até se obter a compensação desejada. No entanto, quando o método se mostra ineficaz, como se verificou em amplificadores de potência baseados em transístores de nitreto de gálio, é difícil saber o que modificar nos sistemas para os tornar de novo úteis. De forma a compreender e desenhar sistemas de pré-distorção digital robustos é necessário, por um lado, perceber o comportamento dos amplificadores de rádio-frequência, por outro, perceber as limitações e relações entre os modelos digitais e o comportamento real do amplificador. Nesse sentido, esta tese explora e descreve estas relações de forma a suportar a escolha de modelos de pré-distorção, desenvolve novos modelos baseados no comportamento dos transístores, e propõe métodos de caracterização para os amplificadores de RF.In current telecommunication systems, the main concern when developing the radio frequency transmitter is power efficiency. This type of design generally leads to a highly nonlinear transmission characteristic, mainly due to the radio frequency power amplifier. This nonlinear transmission severely distorts the information envelope, leading to spectral regrowth, out-of-band distortion. To correct this problem a nonlinear compensation process is employed. For this application, digital predistortion is generally favored for its flexibility and accuracy. Digital predistortion is mostly applied in a blind manner, using brute force until the desired compensation is achieved. Because of this, when the method fails, as it has in gallium nitride based power amplifiers, it is difficult to modify the system to achieve the desired results. To understand and design robust predistortion systems, it is both necessary to have knowledge of the power amplifiers’ behavior, on one hand, and understand the limitations and relations between the digital models and these behaviors, on the other. To do this, this thesis explores and describes these relationships, granting support to the digital predistortion model choice, it further develops new predistortion models based on the physics of the transistors’ behaviors, and it proposes methods for the characterization of radio frequency power amplifiers

Multi Look-Up Table Digital Predistortion for RF Power Amplifier Linearization

Premi extraordinari doctorat curs 2007-2008, àmbit d’Enginyeria de les TICAquesta Tesi Doctoral se centra en el disseny d'un nou linealitzador de Predistorsió Digital (Digital Predistortion - DPD) capaç de compensar la dinàmica i els efectes no lineals introduïts pels Amplificadors de Potència (Power Amplifiers - PAs). Un dels trets més rellevants d'aquest nou predistorsionador digital i adaptatiu consisteix en ser deduïble a partir d'un model de PA anomenat Nonlinear Auto-Regressive Moving Average (NARMA). A més, la seva arquitectura multi-LUT (multi-Taula) permet la implementació en un dispositiu Field Programmable Gate Array (FPGA).La funció de predistorsió es realitza en banda base, per tant, és independent de la banda freqüencial on es durà a terme l'amplificació del senyal de RF, el que pot resultar útil si tenim en compte escenaris multibanda o reconfigurables. D'altra banda, el fet que aquest DPD tingui en compte els efectes de memòria introduïts pel PA, representa una clara millora de les prestacions aconseguides per un simple DPD sense memòria. En comparació amb d'altres DPDs basats en models més computacionalment complexos, com és el cas de les xarxes neuronals amb memòria (Time-Delayed Neural Networks - TDNN), la estructura recursiva del DPD proposat permet reduir el nombre de LUTs necessàries per compensar els efectes de memòria del PA. A més, la seva estructura multi-LUT permet l'escalabilitat, és a dir, activar or desactivar les LUTs que formen el DPD en funció de la dinàmica que presenti el PA.En una primera aproximació al disseny del DPD, és necessari identificar el model NARMA del PA. Un dels majors avantatges que presenta el model NARMA és la seva capacitat per trobar un compromís entre la fidelitat en l'estimació del PA i la complexitat computacional introduïda. Per reforçar aquest compromís, l' ús d'algoritmes heurístics de cerca, com són el Simulated Annealing o els Genetic Algorithms, s'utilitzen per trobar els retards que millor caracteritzen la memòria del PA i per tant, permeten la reducció del nombre de coeficients necessaris per caracteritzar-la. Tot i així, la naturalesa recursiva del model NARMA comporta que, de cara a garantir l'estabilitat final del DPD, cal dur a terme un estudi previ sobre l'estabilitat del model.Una vegada s'ha obtingut el model NARMA del PA i s'ha verificat l'estabilitat d'aquest, es procedeix a l'obtenció de la funció de predistorsió a través del mètode d'identificació predictiu. Aquest mètode es basa en la continua identificació del model NARMA del PA i posteriorment, a partir del model obtingut, es força al PA perquè es comporti de manera lineal. Per poder implementar la funció de predistorsió en la FPGA, cal primer expressar-la en forma de combinacions en paral·lel i cascada de les anomenades Cel·les Bàsiques de Predistorsió (BPCs), que són les unitats fonamentals que composen el DPD. Una BPC està formada per un multiplicador complex, un port RAM dual que actua com a LUT (taula de registres) i un calculador d'adreces. Les LUTs s'omplen tenint en compte una distribució uniforme dels continguts i l'indexat d'aquestes es duu a terme mitjançant el mòdul de l'envoltant del senyal. Finalment, l'adaptació del DPD consisteix en monitoritzar els senyals d'entrada i sortida del PA i anar duent a terme actualitzacions periòdiques del contingut de les LUTs que formen les BPCs. El procés d'adaptació del contingut de les LUTs es pot dur a terme en la mateixa FPGA encarregada de fer la funció de predistorsió, o de manera alternativa, pot ser duta a terme per un dispositiu extern (com per exemple un DSP - Digital Signal Processor) en una escala de temps més relaxada. Per validar l'exposició teòrica i provar el bon funcionalment del DPD proposat en aquesta Tesi, es proporcionen resultats tant de simulació com experimentals que reflecteixen els objectius assolits en la linealització del PA. A més, certes qüestions derivades de la implementació pràctica, tals com el consum de potència o la eficiència del PA, són també tractades amb detall.This Ph.D. thesis addresses the design of a new Digital Predistortion (DPD) linearizer capable to compensate the unwanted nonlinear and dynamic behavior of power amplifiers (PAs). The distinctive characteristic of this new adaptive DPD is its deduction from a Nonlinear Auto Regressive Moving Average (NARMA) PA behavioral model and its particular multi look-up table (LUT) architecture that allows its implementation in a Field Programmable Gate Array (FPGA) device.The DPD linearizer presented in this thesis operates at baseband, thus becoming independent on the final RF frequency band and making it suitable for multiband or reconfigurable scenarios. Moreover, the proposed DPD takes into account PA memory effects compensation which representsan step forward in overcoming classical limitations of memoryless predistorters. Compared to more computational complex DPDs with dynamic compensation, such Time-Delayed Neural Networks (TDNN), this new DPD takes advantage of the recursive nature of the NARMA structure to relax the number of LUTs required to compensate memory effects in PAs. Furthermore, its parallel multi-LUT architecture is scalable, that is, permits enabling or disabling the contribution of specific LUTs depending on the dynamics presented by a particular PA.In a first approach, it is necessary to identify a NARMA PA behavioral model. The extraction of PA behavioral models for DPD linearization purposes is carried out by means of input and output complex envelope signal observations. One of the major advantages of the NARMA structure regards its capacity to deal with the existing trade-off between computational complexity and accuracy in PA behavioral modeling. To reinforce this compromise, heuristic search algorithms such the Simulated Annealing or Genetic Algorithms are utilized to find the best sparse delays that permit accurately reproducing the PA nonlinear dynamic behavior. However, due to the recursive nature of the NARMA model, an stability test becomes a previous requisite before advancing towards DPD linearization.Once the PA model is identified and its stability verified, the DPD function is extracted applying a predictive predistortion method. This identification method relies just on the PA NARMA model and consists in adaptively forcing the PA to behave as a linear device. Focusing in the DPD implementation, it is possible to map the predistortion function in a FPGA, but to fulfill this objective it is first necessary to express the predistortion function as a combined set of LUTs.In order to store the DPD function into a FPGA, it has to be stated in terms of parallel and cascade Basic Predistortion Cells (BPCs), which are the fundamental building blocks of the NARMA based DPD. A BPC is formed by a complex multiplier, a dual port RAM memory block acting as LUT and an address calculator. The LUT contents are filled following an uniform spacing procedure and its indexing is performed with the amplitude (modulus) of the signal's envelope.Finally, the DPD adaptation consists in monitoring the input-output data and performing frequent updates of the LUT contents that conform the BPCs. This adaptation process can be carried out in the same FPGA in charge of performing the DPD function, or alternatively can be performed by an external device (i.e. a DSP device) in a different time-scale than real-time operation.To support all the theoretical design and to prove the linearization performance achieved by this new DPD, simulation and experimental results are provided. Moreover, some issues derived from practical experimentation, such as power consumption and efficiency, are also reported and discussed within this thesis.Award-winningPostprint (published version

Digital Front-End Signal Processing with Widely-Linear Signal Models in Radio Devices

Necessitated by the demand for ever higher data rates, modern communications waveforms have increasingly wider bandwidths and higher signal dynamics. Furthermore, radio devices are expected to transmit and receive a growing number of different waveforms from cellular networks, wireless local area networks, wireless personal area networks, positioning and navigation systems, as well as broadcast systems. On the other hand, commercial wireless devices are expected to be cheap, be relatively small in size, and have a long battery life. The demands for flexibility and higher data rates on one hand, and the constraints on production cost, device size, and energy efficiency on the other, pose difficult challenges on the design and implementation of future radio transceivers. Under these diametric constraints, in order to keep the overall implementation cost and size feasible, the use of simplified radio architectures and relatively low-cost radio electronics are necessary. This notion is even more relevant for multiple antenna systems, where each antenna has a dedicated radio front-end. The combination of simplified radio front-ends and low-cost electronics implies that various nonidealities in the remaining analog radio frequency (RF) modules, stemming from unavoidable physical limitations and material variations of the used electronics, are expected to play a critical role in these devices. Instead of tightening the specifications and tolerances of the analog circuits themselves, a more cost-effective solution in many cases is to compensate for these nonidealities in the digital domain. This line of research has been gaining increasing interest in the last 10-15 years, and is also the main topic area of this work. The direct-conversion radio principle is the current and future choice for building low-cost but flexible, multi-standard radio transmitters and receivers. The direct-conversion radio, while simple in structure and integrable on a single chip, suffers from several performance degrading circuit impairments, which have historically prevented its use in wideband, high-rate, and multi-user systems. In the last 15 years, with advances in integrated circuit technologies and digital signal processing, the direct-conversion principle has started gaining popularity. Still, however, much work is needed to fully realize the potential of the direct-conversion principle. This thesis deals with the analysis and digital mitigation of the implementation nonidealities of direct-conversion transmitters and receivers. The contributions can be divided into three parts. First, techniques are proposed for the joint estimation and predistortion of in-phase/quadrature-phase (I/Q) imbalance, power amplifier (PA) nonlinearity, and local oscillator (LO) leakage in wideband direct-conversion transmitters. Second, methods are developed for estimation and compensation of I/Q imbalance in wideband direct-conversion receivers, based on second-order statistics of the received communication waveforms. Third, these second-order statistics are analyzed for second-order stationary and cyclostationary signals under several other system impairments related to circuit implementation and the radio channel. This analysis brings new insights on I/Q imbalances and their compensation using the proposed algorithms. The proposed algorithms utilize complex-valued signal processing throughout, and naturally assume a widely-linear form, where both the signal and its complex-conjugate are filtered and then summed. The compensation processing is situated in the digital front-end of the transceiver, as the last step before digital-to-analog conversion in transmitters, or in receivers, as the first step after analog-to-digital conversion. The compensation techniques proposed herein have several common, unique, attributes: they are designed for the compensation of frequency-dependent impairments, which is seen critical for future wideband systems; they require no dedicated training data for learning; the estimators are computationally efficient, relying on simple signal models, gradient-like learning rules, and solving sets of linear equations; they can be applied in any transceiver type that utilizes the direct-conversion principle, whether single-user or multi-user, or single-carrier or multi-carrier; they are modulation, waveform, and standard independent; they can also be applied in multi-antenna transceivers to each antenna subsystem separately. Therefore, the proposed techniques provide practical and effective solutions to real-life circuit implementation problems of modern communications transceivers. Altogether, considering the algorithm developments with the extensive experimental results performed to verify their functionality, this thesis builds strong confidence that low-complexity digital compensation of analog circuit impairments is indeed applicable and efficient