Architectural Approaches For Gallium Arsenide Exploitation In High-Speed Computer Design

Continued advances in the capability of Gallium Arsenide (GaAs)technology have finally drawn serious interest from computer system designers. The recent demonstration of very large scale integration (VLSI) laboratory designs incorporating very fast GaAs logic gates herald a significant role for GaAs technology in high-speed computer design:1 In this thesis we investigate design approaches to best exploit this promising technology in high-performance computer systems. We find significant differences between GaAs and Silicon technologies which are of relevance for computer design. The advantage that GaAs enjoys over Silicon in faster transistor switching speed is countered by a lower transistor count capability for GaAs integrated circuits. In addition, inter-chip signal propagation speeds in GaAs systems do not experience the same speedup exhibited by GaAs transistors; thus, GaAs designs are penalized more severely by inter-chip communication. The relatively low density of GaAs chips and the high cost of communication between them are significant obstacles to the full exploitation of the fast transistors of GaAs technology. A fast GaAs processor may be excessively underutilized unless special consideration is given to its information (instructions and data) requirements. Desirable GaAs system design approaches encourage low hardware resource requirements, and either minimize the processor’s need for off-chip information, maximize the rate of off-chip information transfer, or overlap off-chip information transfer with useful computation. We show the impact that these considerations have on the design of the instruction format, arithmetic unit, memory system, and compiler for a GaAs computer system. Through a simulation study utilizing a set of widely-used benchmark programs, we investigate several candidate instruction pipelines and candidate instruction formats in a GaAs environment. We demonstrate the clear performance advantage of an instruction pipeline based upon a pipelined memory system over a typical Silicon-like pipeline. We also show the performance advantage of packed instruction formats over typical Silicon instruction formats, and present a packed format which performs better than the experimental packed Stanford MIPS format

Improving the Immunity of Hybrid SET/MOS Circuits Using Boltzmann Machine Network

Rapid progress in the fabrication technology of silicon nano devices has pushed the device dimension toward 1- 100nm length scale, which renders the basic working principles of CMOS devices more dependent upon quantum effects and doping fluctuations. When device dimensions are scaled down to a few nanometers, quantum effects such as single electron tunneling (SET) and energy quantization lead to interesting new device characteristics that can be exploited to create extremely compact circuits. The SET is one type of nanoscale electronic devices based on quantum tunneling and Coulomb blockade effect, where one or more Coulomb islands are sandwiched between two tunnel junctions which connect respectively with the drain electrode and the source electrode, and are capacitively coupled with one or more gate electrodes. However, both pure SET devices and hybrid SET-MOS circuits face a big problem – the background charges, which influence the accuracy of the circuit. In order to improve their immunity against these charges, we introduce the neuron network ‘Boltzmann machine’ into the circuit. This idea is to improve the accuracy with increasing time redundancy. Single-electron circuits show stochastic behaviors in their operation because of the probabilistic nature of electron tunneling phenomena. They can therefore be successfully used for implementing the stochastic neuron operation of Boltzmann machines. This thesis proposes applications of Boltzmann machine network to improve the immunity of hybrid SET/MOS circuits to overcome random background charges. Detailed unit neuron block and whole neuron network model are used to design hybrid SET/MOS circuits. Two applications based on Boltzmann machine are proposed: (1) Multi-bit A/D converter, and (2) One-bit full adder. Simulation was done using Cadence Spectre simulator with 180nm CMOS model and SET MIB macro model for performance evaluation. And it is expected that our idea can be extended to other hybrid SETMOS

Skybridge: A New Nanoscale 3-D Computing Framework for Future Integrated Circuits

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, continuing the traditional way of scaling to sub-20nm technologies is proving to be very difficult as MOSFETs are reaching their fundamental performance limits [1] and interconnection bottleneck is dominating IC operational power and performance [2]. Migrating to 3-D, as a way to advance scaling, has been elusive due to inherent customization and manufacturing requirements in CMOS architecture that are incompatible with 3-D organization. Partial attempts with die-die [3] and layer-layer [4] stacking have their own limitations [5]. We propose a new 3-D IC fabric technology, Skybridge [6], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge’s core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance/watt benefits, and 10x reduction in interconnect lengths vs. scaled 16-nm CMOS [6]. Fabric-level heat extraction features are found to be effective in managing IC thermal profiles in 3-D. This 3-D integrated fabric proposal overcomes the current impasse of CMOS in a manner that can be immediately adopted, and offers unique solution to continue technology scaling in the 21st century

Circuits and Systems Advances in Near Threshold Computing

Modern society is witnessing a sea change in ubiquitous computing, in which people have embraced computing systems as an indispensable part of day-to-day existence. Computation, storage, and communication abilities of smartphones, for example, have undergone monumental changes over the past decade. However, global emphasis on creating and sustaining green environments is leading to a rapid and ongoing proliferation of edge computing systems and applications. As a broad spectrum of healthcare, home, and transport applications shift to the edge of the network, near-threshold computing (NTC) is emerging as one of the promising low-power computing platforms. An NTC device sets its supply voltage close to its threshold voltage, dramatically reducing the energy consumption. Despite showing substantial promise in terms of energy efficiency, NTC is yet to see widescale commercial adoption. This is because circuits and systems operating with NTC suffer from several problems, including increased sensitivity to process variation, reliability problems, performance degradation, and security vulnerabilities, to name a few. To realize its potential, we need designs, techniques, and solutions to overcome these challenges associated with NTC circuits and systems. The readers of this book will be able to familiarize themselves with recent advances in electronics systems, focusing on near-threshold computing

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved. To evaluate and compare hardware design choices, designers can refer to a myriad of accelerator implementations in the literature. Surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effect of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. It presents the list of optimizations and their quantitative effects as a construction kit, allowing to assess the design choices for each building block separately. Reported optimizations range from up to 10'000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators

Probabilistic-Bits based on Ferroelectric Field-Effect Transistors for Stochastic Computing

A probabilistic-bit (p-bit) is the fundamental building block in the circuit network of a stochastic computing, and it could produce a continuous random bit-stream with tunable probability. Utilizing the stochasticity in few-domain ferroelectric material(FE), we propose for the first time, the p-bits based on ferroelectric FET. The stochasticity of the FE p-bits stems from the thermal noise-induced lattice vibration, which renders dipole fluctuations and is tunable by an external electric field. The impact of several key FE parameters on p-bits' stochasticity is evaluated, where the domain properties are revealed to play crucial roles. Furthermore, the integer factorization based on FE p-bits circuit network is performed to verify its functionality, and the accuracy is found to depend on FE p-bits' stochasticity. The proposed FE p-bits possess the advantages of both extremely low hardware coast and the compatibility with CMOS-technology, rendering it a promising candidate for stochastic computing applications.Comment: 23 pages, 7 figures and supplementary materials with 3 note