Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Efficiency Comparison of Inductor-, Capacitor- and Resonant-based Converters Fully Integrated in CMOS Technology

International audienceThe full integration of DC-DC converters offers great promise for dramatic reduction in power consumption and the number of board-level components in complex systems on chip. Some papers compare the numerous published on-chip and on-die converter structures, but there is the need for an approach to accurately compare the main basic DC-DC conversion topologies. Therefore, this paper presents a method to compare the efficiencies of CMOS integrated capacitive-, inductive-and resonant-based switching converters. The loss mechanism of each structure in hard-switching conditions is detailed and the analytical equations of the power loss and output voltage are given as a function of few CMOS technology parameters. The resulting models can be used to accurately predict converter efficiency in the early design phase, to compare the basic structure in particular the technology node or to orient the passive choice. The proposed method is then applied to design, optimize and compare fully-integrated power delivery requirements on a 1mm 2 on-die area in 65nm CMOS technology over three decades of power density. The results also underline the high efficiency of the promising resonant-based converter. Index Terms—integrated switching power supply, on-chip voltage regulator, switched-capacitor converter, inductive power converter, resonant converte

Dual-Input Switched Capacitor Converter Suitable for Wide Voltage gain Range

International audienceThe capacitive-based switching converter suffers from low efficiency, except for a few conversion ratios, thus limiting its use in fine dynamic voltage and frequency scaling for the power management of digital circuits. Therefore, this paper proposes a Multiple Input Single Output Switched Capacitor Converter (MISO-CSC) to provide flatness efficiency over a large voltage gain range. First, the power efficiency calculation in MISO configuration is given, and then the best ones to optimize the number of switched capacitor structures is selected. By using two power supplies, the MISO converter produces 18 ratios instead of three in SISO (Single Input Single Output) mode. Using a CMOS 65nm technology, the transistor-based simulations exhibit an average 15% efficiency gain over a 0.5-1.4V output voltage range compared to the SISO-CSC. Index Terms— switched capacitor converter, multi-input converter, power efficiency optimization, fully integrated voltage regulator, dynamic voltage and frequency scaling

Fabrication processes and experimental validation of a planar PV power system with monolithically embedded power converters

pre-printThis paper summarizes the research outcome intended to identify the most suitable device architecture and its implementation for cell-level power conversion in a photovoltaic (PV) system. The fabrication process to accommodate the power conditioning unit with the PV cells using the same process run have been presented in this paper. Using this method, the entire converter can be embedded with the PV cells producing AC power directly from the solar cell strings. The initial phase of this project simulated various circuit components in the CMOS process, and the project outcome has been summarized in a previous publication by the authors. This paper presents the experimental results of the proposed process, and a simple chopper circuit has been constructed using the embedded MOSFETs and the PV cells. The circuit has been experimentally characterized, along with components. In addition to the process-related challenges and issues, this paper explains the justification of this integration by achieving higher reliability, portability and complete modular construction for PV-based energy harvesting units. To the knowledge of the authors, no attempt has been made to fabricate power converter components with PV cells in the same process run

Doctor of Philosophy

dissertationMicroelectromechanical systems (MEMS) resonators on Si have the potential to replace the discrete passive components in a power converter. The main intention of this dissertation is to present a ring-shaped aluminum nitride (AlN) piezoelectric microreson

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Design Space Evaluation for Resonant and Hard-charged Switched Capacitor Converters

USB Power Delivery enables a fixed ratio converter to operate over a wider range of output voltages by varying the input voltage. Of the DC/DC step-down converters powered from this type of USB, the hard-charged Switched Capacitor circuit is of interest to industry for its potential high power density. However implementation can be limited by circuit efficiency. In fully resonant mode, the efficiency can be improved while also enabling current regulation. This expands the possible applications into battery chargers and eliminates the need for a two-stage converter.In this work, the trade-off in power loss and area between the hard-charged and fully resonant switched capacitor circuit is explored using a technique that remains agnostic to inductor technology. The loss model for each converter is presented as well as discussion on the restrained design space due to parasitics in the passive components. The results are validated experimentally using GaN-based prototype converters and the respective design spaces are analyzed

Circuit design techniques for Power Efficient Microscale Energy Harvesting Systems

Power Management is considered one of the hot topics nowadays, as it is already known that all integrated circuits need a stable supply with low noise, a constant voltage level across time, and the ability to supply large range of loads. Normal batteries do not provide those specifications. A new concept of energy management called energy harvesting is introduced here. Energy harvesting means collecting power from ambient resources like solar power, Radio Frequency (RF) power, energy from motion...etc. The Energy is collected by means of a transducer that directly converts this energy into electrical energy that can be managed by design to supply different loads. Harvested energy management is critical because normal batteries have to be replaced with energy harvesting modules with power management, in order to make integrated circuits fully autonomous; this leads to a decrease in maintenance costs and increases the life time. This work covers the design of an energy harvesting system focusing on micro-scale solar energy harvesting with power management. The target application of this study is a Wireless Sensor Node/Network (WSN) because its applications are very wide and power management in it is a big issue, as it is very hard to replace the battery of a WSN after deployment. The contribution of this work is mainly shown on two different scopes. The first scope is to propose a new tracking technique and to verify on the system level. The second scope is to propose a new optimized architecture for switched capacitor based power converters. At last, some future recommendations are proposed for this work to be more robust and reliable so that it can be transfered to the production phase. The proposed system design is based on the sub-threshold operation. This design approach decreases the amount of power consumed in the control circuit. It can efficiently harvest the maximum power possible from the photo-voltaic cell and transfer this power to the super-capacitor side with high efficiency. It shows a better performance compared to the literature work. The proposed architecture of the charge pump is more efficient in terms of power capability and knee frequency over the basic linear charge pump topology. Comparison with recent topologies are discussed and shows the robustness of the proposed technique