Impact of Spatial Filtering on Distortion from Low-Noise Amplifiers in Massive MIMO Base Stations

In massive MIMO base stations, power consumption and cost of the low-noise amplifiers (LNAs) can be substantial because of the many antennas. We investigate the feasibility of inexpensive, power efficient LNAs, which inherently are less linear. A polynomial model is used to characterize the nonlinear LNAs and to derive the second-order statistics and spatial correlation of the distortion. We show that, with spatial matched filtering (maximum-ratio combining) at the receiver, some distortion terms combine coherently, and that the SINR of the symbol estimates therefore is limited by the linearity of the LNAs. Furthermore, it is studied how the power from a blocker in the adjacent frequency band leaks into the main band and creates distortion. The distortion term that scales cubically with the power received from the blocker has a spatial correlation that can be filtered out by spatial processing and only the coherent term that scales quadratically with the power remains. When the blocker is in free-space line-of-sight and the LNAs are identical, this quadratic term has the same spatial direction as the desired signal, and hence cannot be removed by linear receiver processing

Efficient offline outer/inner DAC mismatch calibration in wideband ΔΣ ADCs

Distortion due to feedback DAC mismatch is a key limitation in Delta Sigma ADCs for wideband wireless communications. This article presents an efficient frequency-domain mask-based offline mismatch calibration method of both the outer DAC and the inner DACs in a Delta Sigma ADC. The test stimulus for the calibration is a two-tone signal near the band edge. To avoid the need for high-performance signal generation, a frequency mask is applied to void the stimulus signal and its phase noise. In this way, the method is robust against distortion and jitter in the stimulus signal, which therefore could be combined from two low-quality signal generators. The two-tone band-edge signal has the additional benefit that the number of needed samples of the excitation signal is very modest because as many intermodulations as possible contribute to the calculation of the mismatch errors of the DACs. Experimental results confirming the calibration method are obtained from a prototype chip, designed for an 85MHz signal bandwidth in 28nm CMOS technology. A two-tone stimulus around 78 MHz is applied to calculate the mismatch of the outer DAC and the inner DAC with only 68K samples. With the DACs calibrated, an SFDR improvement of 28.1 dB is achieved for a single-tone input at 5 MHz, while for a two-tone input around 71 MHz, the IM3 is improved from -63.6 dBc to below the noise floor (<-94.1 dBc). This illustrates the effectiveness of the approach

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

This document is the Accepted Manuscript version of the following article: Junfeng Zhang, Yang Xu, Zehong Zhang, Yichuang Sun, Zhihua Wang, and Baoyong Chi, ‘A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver’, IEEE Transactions on Microwave Theory and Practice, Vol. 65 (4): 1303-1314, first published online 16 February 2017. The version of record is available online at DOI: 10.1109/TMTT.2017.266237, Published by IEEE. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A fourth-order quadrature bandpass continuous-time sigma-delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital-analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.Peer reviewe

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Digital Solutions for Analog Shortcomings in Delta-Sigma Analog-to-Digital Converters

Portable, high power efficiency communication devices is a growing market in the semiconductor industry. Analog-to-digital converters (ADC) are key interface that are used to digitize the sensed information. Recently, digital techniques have been proposed to improve analog building block power efficiency in sub-micron technologies. This research focuses on mixed signal approaches to improve the power efficiency of the noise shaping ADCs and mitigate analog inaccuracies such as non-linearity and mismatch. First, a novel continuous-time filtering delta-sigma ADC is proposed to save power and area. Digital techniques have been proposed to make the architecture more robust to out-of-band unwanted signals. A prototype was fabricated in a 65 nm CMOS technology achieving an SNDR of 72.4 dB operating at 250 MHz sampling frequency over 7 MHz bandwidth, with a power consumption of 16.3 mW. Next, A novel digital circuitry is proposed to improve the tolerance of a discrete-time delta sigma ADC to mismatch and enhance the resolution of an ADC in the presence of mismatch. A custom IC was fabricated in a 65 nm CMOS technology consuming 40.4 μA from a 1 V supply. It achieves 76.18 dB SNDR operating at 1.2 MHz sampling frequency and 25 kHz signal bandwidth

Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator

The demand for higher data rates in receivers with carrier aggregation (CA) such as LTE, increases the efforts to integrate large number of wireless services into single receiving path, so it needs to digitize the signal in intermediate or high frequencies. It relaxes most of the front-end blocks but makes the design of ADC very challenging. Solving the bottleneck associated with ADC in receiver architecture is a major focus of many ongoing researches. Recently, continuous time Sigma-Delta analog-to-digital converters (ADCs) are getting more attention due to their inherent filtering properties, lower power consumption and wider input bandwidth. But, it suffers from several non-idealities such as clock jitter and ELD which decrease the ADC performance. This dissertation presents two projects that address CT-ΣΔ modulator non-idealities. One of the projects is a CT- ΣΔ modulator with 10.9 Effective Number of Bits (ENOB) with Gradient Descent (GD) based calibration technique. The GD algorithm is used to extract loop gain transfer function coefficients. A quantization noise reduction technique is then employed to improve the Signal to Quantization Noise Ratio (SQNR) of the modulator using a 7-bit embedded quantizer. An analog fast path feedback topology is proposed which uses an analog differentiator in order to compensate excess loop delay. This approach relaxes the requirements of the amplifier placed in front of the quantizer. The modulator is implemented using a third order loop filter with a feed-forward compensation paths and a 3-bit quantizer in the feedback loop. In order to save power and improve loop linearity a two-stage class-AB amplifier is developed. The prototype modulator is implemented in 0.13μm CMOS technology, which achieves peak Signal to Noise and Distortion Ratio (SNDR) of 67.5dB while consuming total power of 8.5-mW under a 1.2V supply with an over sampling ratio of 10 at 300MHz sampling frequency. The prototype achieves Walden's Figure of Merit (FoM) of 146fJ/step. The second project addresses clock jitter non-ideality in Continuous Time Sigma Delta modulators (CT- ΣΔM), the modulator suffer from performance degradation due to uncertainty in timing of clock at digital-to-analog converter (DAC). This thesis proposes to split the loop filter into two parts, analog and digital part to reduce the sensitivity of feedback DAC to clock jitter. By using the digital first-order filter after the quantizer, the effect of clock jitter is reduced without changing signal transfer function (STF). On the other hand, as one pole of the loop filter is implemented digitally, the power and area are reduced by minimizing active analog elements. Moreover, having more digital blocks in the loop of CT- ΣΔM makes it less sensitive to process, voltage, and temperature variations. We also propose the use of a single DAC with a current divider to implement feedback coefficients instead of two DACs to decrease area and clock routing. The prototype is implemented in TSMC 40 nm technology and occupies 0.06 mm^2 area; the proposed solution consumes 6.9 mW, and operates at 500 MS/s. In a 10 MHz bandwidth, the measured dynamic range (DR), peak signal-to-noise-ratio (SNR), and peak signal-to-noise and distortion (SNDR) ratios in presence of 4.5 ps RMS clock jitter (0.22% clock period) are 75 dB, 68 dB, and 67 dB, respectively. The proposed structure is 10 dB more tolerant to clock jitter when compared to the conventional ΣΔM design for similar loop filter

Blocker Tolerant Radio Architectures

Future radio platforms have to be inexpensive and deal with a variety of co- existence issues. The technology trend during the last few years is towards system- on-chip (SoC) that is able to process multiple standards re-using most of the digital resources. A major bottle-neck to this approach is the co-existence of these standards operating at different frequency bands that are hitting the receiver front-end. So the current research is focused on the power, area and performance optimization of various circuit building blocks of a radio for current and incoming standards. Firstly, a linearization technique for low noise amplifiers (LNAs) called, Robust Derivative Superposition (RDS) method is proposed. RDS technique is insensitive to Process Voltage and Temperature (P.V.T.) variations and is validated with two low noise transconductance amplifier (LNTA) designs in 0.18µm CMOS technology. Measurement results from 5 dies of a resistive terminated LNTA shows that the pro- posed method improves IM3 over 20dB for input power up to -18dBm, and improves IIP_(3) by 10dB. A 2V inductor-less broadband 0.3 to 2.8GHz balun-LNTA employing the proposed RDS linearization technique was designed and measured. It achieves noise figure of 6.5dB, IIP3 of 16.8dBm, and P1dB of 0.5dBm having a power consumption of 14.2mW. The balun LNTA occupies an active area of 0.06mm2. Secondly, the design of two high linearity, inductor-less, broadband LNTAs employing noise and distortion cancellation techniques is presented. Main design issues and the performance trade-offs of the circuits are discussed. In the fully differential architecture, the first LNTA covers 0.1-2GHz bandwidth and achieves a minimum noise figure (NFmin) of 3dB, IIP_(3) of 10dBm and a P_(1dB) of 0dBm while dissipating 30.2mW. The 2^(nd) low power bulk driven LNTA with 16mW power consumption achieves NFmin of 3.4dB, IIP3 of 11dBm and 0.1-3GHz bandwidth. Each LNTA occupy an active area of 0.06mm2 in 45nm CMOS. Thirdly, a continuous-time low-pass ∆ΣADC equipped with design techniques to provide robustness against loop saturation due to blockers is presented. Loop over- load detection and correction is employed to improve the ADC’s tolerance to blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADC’s blocker tolerance, a minimally-invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. An ADC prototype is implemented in a 90nm CMOS technology and experimentally it achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500MHz and 17.1mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5dBFS while the conventional feed-forward modulator becomes unstable at -23.5dBFS of blocker power. The proposed blocker rejection techniques are minimally-invasive and take less than 0.3µsec to settle after a strong agile blocker appears. Finally, a new radio partitioning methodology that gives robust analog and mixed signal radio development in scaled technology for SoC integration, and the co-design of RF FEM-antenna system is presented. Based on the proposed methodology, a CMOS RF front-end module (FEM) with power amplifier (PA), LNA and transmit/receive switch, co-designed with antenna is implemented. The RF FEM circuit is implemented in a 32nm CMOS technology. Post extracted simulations show a noise figure < 2.5dB, S_(21) of 14dB, IIP3 of 7dBm and P1dB of -8dBm for the receiver. Total power consumption of the receiver is 11.8mW from a 1V supply. On the trans- mitter side, PA achieves peak RF output power of 22.34dBm with peak power added efficiency (PAE) of 65% and PAE of 33% with linearization at -6dB power back off. Simulations show an efficiency of 80% for the miniaturized dipole antenna

Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications

Software-defined radio receivers (SDRs) have become popular to accommodate multi-standard wireless services using a single chip-set solution in mobile telecommunication systems. In SDRs, the signal is down-converted to an intermediate frequency and then digitalized. This approach relaxes the specifications for most of the analog front-end building blocks by performing most of the signal processing in the digital domain. However, since the analog-to-digital converter (ADC) is located as close as possible to the antenna in SDR architectures, the ADC specification requirements are very stringent because a large amount of interference signals are present at the ADC input due to the removal of filtering blocks, which particularly affects the dynamic range (DR) specification. Sigma-delta (ΣΔ) ADCs have several benefits such as low implementation cost, especially when the architecture contains mostly digital circuits. Furthermore, continuous-time (CT) ΣΔ ADCs allow elimination of the anti‐aliasing filter because input signals are sampled after the integrator. The bandwidth requirements for the amplifiers in CT ΣΔ ADCs can be relaxed due to the continuous operation without stringing settling time requirements. Therefore, they are suitable for high‐speed and low‐power applications. In addition, CT ΣΔ ADCs achieve high resolution due to the ΣΔ modulator’s noise shaping property. However, the in-band quantization noise is shaped by the analog loop filter and the distortions of the analog loop filter directly affect the system output. Hence, highly linear low-noise loop filters are required for high-performance ΣΔ modulators. The first task in this research focused on using CMOS 90 nm technology to design and fabricate a 5^(TH)–order active-RC loop filter with a cutoff frequency of 20 MHz for a low pass (LP) CT ΣΔ modulator. The active-RC topology was selected because of the high DR requirement in SDR applications. The amplifiers in the first stage of the loop filter were implemented with linearization techniques employing anti-parallel cancellation and source degeneration in the second stage of the amplifiers. These techniques improve the third-order intermodulation (IM3) by approximately 10 dB; while noise, area, and power consumption do not increase by more than 10%. Second, a current-mode adder-flash ADC was also fabricated as part of a LP CT ΣΔ modulator. The new current-mode operation developed through this research makes possible a 53% power reduction. The new technology also lessens existing problems associated with voltage-mode flash ADCs, which are mainly related to voltage headroom restrictions, speed of operation, offsets, and power efficiency of the latches. The core of the current-mode adder-flash ADC was fabricated in CMOS 90 nm technology with 1.2 V supply; it dissipates 3.34 mW while operating at 1.48 GHz and consumes a die area of 0.0276 mm^(2). System-on chip (SoC) solutions are becoming more popular in mobile telecommunication systems to improve the portability and competitiveness of products. Since the analog/RF and digital blocks often share the same external power supply in SoC solutions, the on-chip generation of clean power supplies is necessary to avoid system performance degradation due to supply noises. Finally, the critical design issues for external capacitor-less low drop-out (LDO) regulators for SoC applications are addressed in this dissertation, especially the challenges related to power supply rejection at high frequencies as well as loop stability and transient response. The paths of the power supply noise to the LDO output were analyzed, and a power supply noise cancellation circuit was developed. The power supply rejection (PSR) performance was improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. Fabricated in a 0.18 μm CMOS technology with 1.8 V supply, the entire proposed LDO consumes 55 μA of quiescent current while in standby operation, and it has a drop-out voltage of 200 mV when providing 50 mA to the load. Its active core chip area is 0.14 mm2. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively

Receiver Front-Ends in CMOS with Ultra-Low Power Consumption

Historically, research on radio communication has focused on improving range and data rate. In the last decade, however, there has been an increasing demand for low power and low cost radios that can provide connectivity with small devices around us. They should be able to offer basic connectivity with a power consumption low enough to function extended periods of time on a single battery charge, or even energy scavenged from the surroundings. This work is focused on the design of ultra-low power receiver front-ends intended for a receiver operating in the 2.4GHz ISM band, having an active power consumption of 1mW and chip area of 1mm². Low power consumption and small size make it hard to achieve good sensitivity and tolerance to interference. This thesis starts with an introduction to the overall receiver specifications, low power radio and radio standards, front-end and LO generation architectures and building blocks, followed by the four included papers. Paper I demonstrates an inductorless front-end operating at 915MHz, including a frequency divider for quadrature LO generation. An LO generator operating at 2.4GHz is shown in Paper II, enabling a front-end operating above 2GHz. Papers III and IV contain circuits with combined front-end and LO generator operating at or above the full 2.45GHz target frequency. They use VCO and frequency divider topologies that offer efficient operation and low quadrature error. An efficient passive-mixer design with improved suppression of interference, enables an LNA-less design in Paper IV capable of operating without a SAW-filter

Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers

The quest for multi-standard and software-defined radio (SDR) receivers calls for high flexibility in the receiver building-blocks so that to accommodate several wireless services using a single receiver chain in mobile handsets. A potential approach to achieve flexibility in the receiver is to move the analog-to-digital converter (ADC) closer to the antenna so that to exploit the enormous advances in digital signal processing, in terms of technology scaling, speed, and programmability. In this context, continuous-time (CT) delta-sigma (ΔƩ) ADCs show up as an attractive option. CT ΔƩ ADCs have gained significant attention in wideband receivers, owing to their amenability to operate at a higher-speed with lower power consumption compared to discrete-time (DT) implementations, inherent anti-aliasing, and robustness to sampling errors in the loop quantizer. However, as the ADC moves closer to the antenna, several blockers and interferers are present at the ADC input. Thus, it is important to investigate the sensitivities of CT ΔƩ ADCs to out-of-band (OOB) blockers and find the design considerations and solutions needed to maintain the performance of CT ΔƩ modulators in presence of OOB blockers. Also, CT ΔƩ modulators suffer from a critical limitation due to their high sensitivity to the clock-jitter in the feedback digital-to-analog converter (DAC) sampling-clock. In this context, the research work presented in this thesis is divided into two main parts. First, the effects of OOB blockers on the performance of CT ΔƩ modulators are investigated and analyzed through a detailed study. A potential solution is proposed to alleviate the effect of noise folding caused by intermodulation between OOB blockers and shaped quantization noise at the modulator input stage through current-mode integration. Second, a novel DAC solution that achieves tolerance to pulse-width jitter by spectrally shaping the jitter induced errors is presented. This jitter-tolerant DAC doesn’t add extra requirements on the slew-rate or the gain-bandwidth product of the loop filter amplifiers. The proposed DAC was implemented in a 90nm CMOS prototype chip and provided a measured attenuation for in-band jitter induced noise by 26.7dB and in-band DAC noise by 5dB, compared to conventional current-steering DAC, and consumes 719µwatts from 1.3V supply