A New and Efficient Method of Designing Low Noise Microwave Oscillators

Die Dimensionierung von Mikrowellen-Oszillatoren war und ist das Thema vieler Veröffentlichungen. Zu einem gewissen Grade wurden Oszillatoren primär aufgrund experimenteller Daten und Erfahrungen gebaut und deren Eigenschaften dann gemessen und die Daten veröffentlicht. Von der Anwenderseite her ist es jedoch wichtig und sinnvoll, dass man von einem Satz Spezifikationen ausgeht und dann eine Synthese-Prozedur hat, die zur erfolgreichen Schaltung führt. Im Rahmen dieser Dissertation wurde zunächst einmal die vorhandene internationale Literatur untersucht und dahin geprüft, welche Ansätze zum optimalen Design vorhanden sind. Hier werden die entsprechenden Literaturstellen aufgeführt und kommentiert. Einer der beliebtesten Oszillatorschaltungen ist die Colpitts-Schaltung. Diese wird im Rahmen der Dissertation genauer untersucht, wobei zunächst das Kleinsignalverhalten betrachtet wird und dann das Großsignalverhalten ausführlich dargestellt wird. Es werden Mikrowellen Bipolar-Transistoren verwendet, da sich deren Großsignalparameter stärker ändert als die von Feldeffekttransistoren. Es folgt sodann eine Darstellung des Rauschens innerhalb des Transistors. Der Kern der Arbeit stellt eine mathematische Analyse dar, die es gestattet, sowohl das Großsignalverhalten als auch das Rauschen des Oszillators zu berechnen, wobei erstmalig in der Literatur das Verhalten der Ausgangsleistung und des Rauschens des Oszillators genau betrachtet wird und für beides der beste Arbeitspunkt berechnet wurde. Um dieses zu unterstützen, wurden gleichzeitig verfügbare Resonatoren angesprochen und die Messung des Großsignalverhaltens des Transistors sowie die Messung des Phasenrauschens dargestellt. Nach der mathematischen Darstellung des Problems wurden eine Reihe von Oszillatoren nach dem Schema aufgebaut und vermessen. Es zeigt sich eine exzellente Übereinstimmung zwischen der Messung, der Synthese-Berechnung, die auch eine Analyse beinhaltet und einer vollen HB-Analyse mit einem kommerziellen Simulator. Insgesamt wurden drei Methode zur Rauschberechnung und Optimierung dargestellt. 1. Eine Erweiterung der Leeson-Formel mit exakter Berechnung aller notwendigen Parameter. 2. Die Berechnung des zur Entdämpfung notwendigen negativen Widerstandes des Oszillators im Zeitbereich unter Einbeziehung seines Rauschens. 3. Die Rausch-Berechnung des Oszillators mit allen Rauschbeiträgen des Oszillators als Regelschleifen-Problem. Die Arbeit wird abgerundet durch drei diskrete Beispiele im Anhang, bei denen die generelle Berechnung des Oszillators das Verhalten im Großsignalbereich und abschließend die Berechnung eines optimierten Oszillators mit allen parasitären Elementen durchgeführt wurde.How to design microwave oscillators has been and is the subject of many publications. To a certain degree oscillators had been designed based on experimental data and experiences and the resulting performance has been measured and published. The designer, however, considers it important and useful to start from a set of specifications and then applies a synthesis procedure, which leads to a successful circuit. Within the scope of this dissertation, the existing literature has been searched to find which successful and optimum design-procedures were published. The relevant literature is referenced and commented. One of the more favorable oscillator circuits is the Colpitts circuit. This dissertation takes a closer look at it, starting with a small signal performance and then the large signal performance is discussed in detail. Since the large signal parameters deviate further from the small signal parameters, microwave bipolar transistors are being used rather than field-effect transistors. Next is a discussion of the noise of a transistor. The core of the work is a mathematical analysis, which allows to calculate both large signal performance and noise performance whereby as a first the output power and the noise are simultaneously considered and the optimum bias point is found. In order to support this, various resonators are discussed. The measurement of large signal parameters of the transistor is shown and finally phase noise measurements are presented. Following the mathematical solution of the problem, various oscillators had been built following this procedure and were measured. There is an excellent agreement between measurement and this synthesis calculation, which also contains an analysis. An excellent agreement is also found using a HB-based commercial simulator. In total three methods to calculate the phase noise and obtain best performance are demonstrated. 1.An extension of the Leeson formula with exact calculation of all necessary parameters. 2.The calculation of the negative noisy resistance necessary to start oscillation is calculated in time domain. 3.Noise calculation of an oscillator including all noises as a loop problem. This work finishes by showing three discrete cases in the appendix. Here the oscillators general performance is calculated using large signal conditions and finally an optimized oscillator with all parasitic elements is shown

SiGe based multiple-phase VCO operating for mm-wave frequencies

The ever-increasing demand for higher speed in wireless consumer applications has increased the interest in the unlicensed spectrum of 7 GHz around 60 GHz. The high atmospheric oxygen absorption at 60 GHz and small size of the antennas at this frequency requires the use of integrated phased-array systems to overcome the deficiencies of lossy channels at these frequencies. The phased arrays combine signals from multiple paths to obtain higher receiver sensitivity and directivity. The system thus requires phase-shifted voltage-controlled oscillator (VCO) signals to implement phase shifting in the local-oscillator (LO) path. In this research, the vector sum method to generate various phases of the signal at 60 GHz was investigated for its suitability in phased-array systems. The main focus was on improving the phase noise performance of the VCO. The VCO was implemented using a fully differential common-collector Colpitts oscillator in the cascode configuration, which was found to be the VCO configuration with acceptable phase noise performance and stability in the millimetre-wave range. The research focus was on modelling the phase noise of the VCO, and was performed by identifying the impulse sensitivity function for various noise sources, followed by analysing its effect on the linear time varying (LTV) model of the oscillators. The analysis led to a closed-form expression for the phase noise of the oscillator in terms of process and design parameters. The design was then optimised in terms of identified parameters to attain minimum phase noise. The phase noise expression using LTV theory and SpectreRF simulations reported the same optimum value for the design parameter, of around 0.3 for the capacitor ratio. The simulation results utilising the vector sum phase shifting method to generate multiple phase oscillator signals suggest its suitability in implementing phased-array systems in the millimetre-wave range. The vector sum was realised by generating quadrature signals from the oscillator using hybrid couplers. Variable gain amplifiers (VGAs) based on Gilbert mixer topology were used to combine the in-phase and quadrature phase signals to generate the phase-shifted oscillator signal. The gains of the VGAs were linearised by using a pre-distortion circuit, which was an inverse tanh cell. A fully differential 60 GHz VCO was fabricated using a SiGe process with a fT of 200 GHz. The fabricated integrated circuit (IC) measured at the wafer level had a centre frequency of 52.8 GHz and a tuning range of 7 GHz. It demonstrated a phase noise performance of -98.9 dBc/Hz at 1 MHz offset and a power dissipation of 140 mW, thus providing a VCO figure of merit of 172 dBc/Hz. It delivered a differential output power of 8 dBm and the IC occupied an area of 0.54 mm2, including the bondpads. It was thus concluded that a 10 % design margin for the tuning range is required while using SiGe BiCMOS technology. The simulation results demonstrate that the VCO, along with an active interpolator, provides a range of phase-shifted signals from 0° to 360° in steps of 22.5° for various gain settings of the VGAs. The power dissipation of the active interpolator is around 60 mW and the system could thus be employed in LO path shifting architecture of the phased arrays with increased power consumption.Thesis (PhD)--University of Pretoria, 2013.Electrical, Electronic and Computer Engineeringunrestricte

Ka-band Ga-As FET noise receiver/device development

The development of technology for a 30 GHz low noise receiver utilizing GaAs FET devices exclusively is discussed. This program required single and dual-gate FET devices, low noise FET amplifiers, dual-gate FET mixers, and FET oscillators operating at Ka-band frequencies. A 0.25 micrometer gate FET device, developed with a minimum noise figure of 3.3 dB at 29 GHz and an associated gain of 7.4 dB, was used to fabricate a 3-stage amplifier with a minimum noise figure and associated gain of 4.4 dB and 17 dB, respectively. The 1-dB gain bandwidth of this amplifier extended from below 26.5 GHz to 30.5 GHz. A dual-gate mixer with a 2 dB conversion loss and a minimum noise figure of 10 dB at 29 GHz as well as a dielectric resonator stabilized FET oscillator at 25 GHz for the receiver L0. From these components, a hybrid microwave integrated circuit receiver was constructed which demonstrates a minimum single-side band noise figure of 4.6 dB at 29 GHz with a conversion gain of 17 dB. The output power at the 1-dB gain compression point was -5 dBm

Application of the polar loop technique to UHF SSB transmitters

SIGLEAvailable from British Library Document Supply Centre- DSC:D68470/86 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Investigation on LIGA-MEMS and on-chip CMOS capacitors for a VCO application

Modern communication systems require high performance radio frequency (RF) and microwave circuits and devices. This is becoming increasingly challenging to realize in the content of cost/size constraints. Integrated circuits (ICs) satisfy the cost/size requirement, but performance is often sacri¯ced. For instance, high quality factor (Q factor) passive components are difficult to achieve in standard silicon-based IC processes.In recent years, microelectromechanical systems (MEMS) devices have been receiving increasing attention as a possible replacement for various on-chip passive elements, offering potential improvement in performance while maintaining high levels of integration. Variable capacitors (varactor) are common elements used in various applications. One of the MEMS variable capacitors that has been recently developed is built using deep X-ray lithography (as part of the LIGA process). This type of capacitor exhibits high quality factor at microwave frequencies.The complementary metal oxide semiconductor (CMOS) technology dominates the silicon IC process. CMOS becomes increasingly popular for RF applications due to its advantages in level of integration, cost and power consumption. This research demonstrates a CMOS voltage-controlled oscillator (VCO) design which is used to investigate methods, advantages and problems in integrating LIGA-MEMS devices to CMOS RF circuits, and to evaluate the performance of the LIGA-MEMS variable capacitor in comparison with the conventional on-chip CMOS varactor. The VCO was designed and fabricated using TSMC 0.18 micron CMOS technology. The core of the VCO, including transistors, resistors, and on-chip inductors was designed to connect to either an on-chip CMOS varactor or an off-chip LIGA-MEMS capacitor to oscillate between 2.6 GHz and 2.7 GHz. Oscillator phase noise analysis is used to compare the performance between the two capacitors. The fabricated VCO occupied an area of 1 mm^2.This initial attempt at VCO fabrication did not produce a functional VCO, so the performance of the capacitors with the fabricated VCO could not be tested. However, the simulation results show that with this LIGA-MEMS capacitor, a 6.4 dB of phase noise improvement at 300 kHz offset from the carrier is possible in a CMOS-based VCO design

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

Circuit design and technological limitations of silicon RFICs for wireless applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 201-206).Semiconductor technologies have been a key to the growth in wireless communication over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power dissipation. A better understanding of how an IC technology affects critical RF signal chain components will greatly aid the design of wireless systems and the development of process technologies for the increasingly complex applications that lie on the horizon. Many of the evolving applications will embody the concept of adaptive performance to extract the maximum capability from the RF link in terms of bandwidth, dynamic range, and power consumption-further engaging the interplay of circuits and devices is this design space and making it even more difficult to discern a clear guide upon which to base technology decisions. Rooted in these observations, this research focuses on two key themes: 1) devising methods of implementing RF circuits which allow the performance to be dynamically tuned to match real-time conditions in a power-efficient manner, and 2) refining approaches for thinking about the optimization of RF circuits at the device level. Working toward a 5.8 GHz receiver consistent with 1 GBit/s operation, signal path topologies and adjustable biasing circuits are developed for low-noise amplifiers (LNAs) and voltage-controlled oscillators (VCOs) to provide a facility by which power can be conserved when the demand for sensitivity is low. As an integral component in this effort, tools for exploring device level issues are illustrated with both circuit types, helping to identify physical limitations and design techniques through which they can be mitigated.(cont.) The design of two LNAs and four VCOs is described, each realized to provide a fully-integrated solution in a 0.5 tm SiGe BiCMOS process, and each incorporating all biasing and impedance matching on chip. Measured results for these 5-6GHz circuits allow a number of poignant technology issues to be enlightened, including an exhibition of the importance of terminal resistances and capacitances, a demonstration of where the transistor fT is relevant and where it is not, and the most direct comparison of bipolar and CMOS solutions offered to date in this frequency range. In addition to covering a number of new circuit techniques, this work concludes with some new views regarding IC technologies for RF applications.by Donald A. Hitko.Ph.D

A Low-Power BFSK/OOK Transmitter for Wireless Sensors

In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation

Lithium niobate RF-MEMS oscillators for IoT, 5G and beyond

This dissertation focuses on the design and implementation of lithium niobate (LiNbO3) radiofrequency microelectromechanical (RF-MEMS) oscillators for internet-of-things (IoT), 5G and beyond. The dissertation focuses on solving two main problems found nowadays in most of the published works: the narrow tuning range and the low operating frequency (sub 3 GHz) acoustic oscillators currently deliver. The work introduced here enables wideband voltage-controlled MEMS oscillators (VCMOs) needed for emerging applications in IoT. Moreover, it enables multi-GHz (above 8 GHz) RF-MEMS oscillators through harnessing over mode resonances for 5G and beyond. LiNbO3 resonators characterized by high-quality factor (Q), high electromechanical coupling (kt2), and high figure-of-merit (FoMRES= Q kt2) are crucial for building the envisioned high-performance oscillators. Those oscillators can be enabled with lower power consumption, wider tuning ranges, and a higher frequency of oscillation when compared to other state-of-the-art (SoA) RF-MEMS oscillators. Tackling the tuning range issue, the first VCMO based on the heterogeneous integration of a high Q LiNbO3 RF-MEMS resonator and complementary metal-oxide semiconductor (CMOS) is demonstrated in this dissertation. A LiNbO3 resonator array with a series resonance of 171.1 MHz, a Q of 410, and a kt2 of 12.7% is adopted, while the TSMC 65 nm RF LP CMOS technology is used to implement the active circuitry with an active area of 220×70 µm2. Frequency tuning of the VCMO is achieved by programming a binary-weighted digital capacitor bank and a varactor that are both connected in series to the resonator. The measured best phase noise performances of the VCMO are -72 and -153 dBc/Hz at 1 kHz and 10 MHz offsets from 178.23 and 175.83 MHz carriers, respectively. The VCMO consumes a direct current (DC) of 60 µA from a 1.2 V supply while realizing a tuning range of 2.4 MHz (~ 1.4% tuning range). Such VCMOs can be applied to enable ultralow-power, low phase noise, and wideband RF synthesis for emerging applications in IoT. Moreover, the first VCMO based on LiNbO3 lateral overtone bulk acoustic resonator (LOBAR) is demonstrated in this dissertation. The LOBAR excites over 30 resonant modes in the range of 100 to 800 MHz with a frequency spacing of 20 MHz. The VCMO consists of a LOBAR in a closed-loop with two amplification stages and a varactor-embedded tunable LC tank. By the bias voltage applied to the varactor, the tank can be tuned to change the closed-loop gain and phase responses of the oscillator so that Barkhausen’s conditions are satisfied for the targeted resonant mode. The tank is designed to allow the proposed VCMO to lock to any of the ten overtones ranging from 300 to 500 MHz. These ten tones are characterized by average Qs of 2100, kt2 of 1.5%, FoMRES of 31.5 enabling low phase noise, and low-power oscillators crucial for IoT. Owing to the high Qs of the LiNbO3 LOBAR, the measured VCMO shows a close-in phase noise of -100 dBc/Hz at 1 kHz offset from a 300 MHz carrier and a noise floor of -153 dBc/Hz while consuming 9 mW. With further optimization, this VCMO can lead to direct RF synthesis for ultra-low-power transceivers in multi-mode IoT nodes. Tackling the multi-GHz operation problem, the first Ku-band RF-MEMS oscillator utilizing a third antisymmetric overtone (A3) in a LiNbO3 resonator is presented in the dissertation. Quarter-wave resonators are used to satisfy Barkhausen’s oscillation conditions for the 3rd overtone while suppressing the fundamental and higher-order resonances. The oscillator achieves measured phase noise of -70 and -111 dBc/Hz at 1 kHz and 100 kHz offsets from a 12.9 GHz carrier while consuming 20 mW of dc power. The oscillator achieves a FoMOSC of 200 dB at 100 kHz offset. The achieved oscillation frequency is the highest reported to date for a MEMS oscillator. In addition, this dissertation introduces the first X-band RF-MEMS oscillator built using CMOS technology. The oscillator consists of an acoustic resonator in a closed loop with cascaded RF tuned amplifiers (TAs) built on TSMC RF GP 65 nm CMOS. The TAs bandpass response, set by on-chip inductors, satisfies Barkhausen's oscillation conditions for A3 only. Two circuit variations are implemented. The first is an 8.6 GHz standalone oscillator with a source-follower buffer for direct 50 Ω-based measurements. The second is an oscillator-divider chain using an on-chip 3-stage divide-by-2 frequency divider for a ~1.1 GHz output. The standalone oscillator achieves measured phase noise of -56, -113, and -135 dBc/Hz at 1 kHz, 100 kHz, and 1 MHz offsets from an 8.6 GHz output while consuming 10.2 mW of dc power. The oscillator also attains a FoMOSC of 201.6 dB at 100 kHz offset, surpassing the SoA electromagnetic (EM) and RF-MEMS based oscillators. The oscillator-divider chain produces a phase noise of -69.4 and -147 dBc/Hz at 1 kHz and 1 MHz offsets from a 1075 MHz output while consuming 12 mW of dc power. Its phase noise performance also surpasses the SoA L-band phase-locked loops (PLLs). The demonstrated performance shows the strong potential of microwave acoustic oscillators for 5G frequency synthesis and beyond. This work will enable low-power 5G transceivers featuring high speed, high sensitivity, and high selectivity in small form factors