Comparative study of the MASH digital delta-sigma modulators

The paper focuses on the Multi-stAge noise SHaping (MASH) digital delta-sigma modulator (DDSM) that employs multi-moduli (MM-MASH). Different architectures of the MASH DDSM are compared. In particular, it is proven that a higherorder error feedback modulator (EFM) has the same sequence length as a first-order EFM (EFM1) in an MM-MASH. In addition, the method that is required to setup the quantisation moduli of the MM-MASH is introduced. The theory is validated by simulation

Estimation of an initial condition of sigma-delta modulators via projection onto convex sets

Abstract—In this paper, an initial condition of strictly causal rational interpolative sigma-delta modulators (SDMs) is estimated based on quantizer output bit streams and an input signal. A set of initial conditions generating bounded trajectories is characterized. It is found that a set of initial conditions generating bounded trajectories but not necessarily corresponding to quantizer output bit streams is convex. Also, it is found that a set of initial conditions corresponding to quantizer output bit streams but not necessarily generating bounded trajectories is convex too. Moreover, it is found that an initial condition both corresponding to quantizer output bit streams and generating bounded trajectories is uniquely defined if the loop filter is unstable (Here, an unstable loop filter refers to that with at least one of its poles being strictly outside the unit circle). To estimate that unique initial condition, a projection onto convex set approach is employed. Numerical computer simulations show that the employed method can estimate the initial condition effectively

Prediction of the Spectrum of a Digital Delta–Sigma Modulator Followed by a Polynomial Nonlinearity

This paper presents a mathematical analysis of the power spectral density of the output of a nonlinear block driven by a digital delta-sigma modulator. The nonlinearity is a memoryless third-order polynomial with real coefficients. The analysis yields expressions that predict the noise floor caused by the nonlinearity when the input is constant

A method for searching the limit cycles of high order Sigma-Delta modulators

In this paper an approach for description and validation of potential limit cycles of high order sigma-delta modulators is presented. The approach is based on a parallel decomposition of the modulator. In this representation, the general N-th order modulator is transformed into a decomposition of low order, generally complex modulators, which interact only through the quantizer function. The decomposition considered helps to describe easily the time domain behavior of the modulator. Based on this, the conditions for the existence of limit cycles in the high order modulator for constant inputs, are obtained. They are determined by the periodicity conditions for the states of the first order modulators. In this case, the state variables are uncoupled and the obtained conditions are very easy to be checked. Limit cycles correspond to periodic output sequences and the proposed method includes description and validation of possible sequences

Nonlinear Model-Based Approach for Accurate Stability Prediction of One-Bit Higher-Order Delta-Sigma (Δ-Σ)Modulators

The present approaches on predicting stability of Delta-Sigma (Δ-Σ) modulators are mostly confined to DC inputs. This poses limitations as practical applications of Δ-Σ modulators involve a wide range of signals other than DC. In this paper, a quasi-linear model for Δ-Σ modulators with nonlinear feedback control analysis is presented that accurately predicts the stability of higher-order single-loop 1-bit Δ-Σ modulators for various types of input signals such as single-sinusoids, dual-sinusoids, multiple-sinusoids and Gaussian. Theoretical values are shown to match closely with simulation results. The results of this paper would significantly speed up the design and evaluation of higher-order single-loop 1-bit Δ-Σ modulators for various applications including those that may require multiple-sinusoidal inputs or any general input composed of a finite number of sinusoidal components, circumventing the need to perform detailed time-consuming simulations to quantify stability limits. By using the proposed method, the difference between the predicted and the actual stable amplitude limits results in an error of less than 1 dB in the in-band Signal-to-Noise Ratio (SNR) for 3rd- and higher-order Δ-Σ modulators for single-sinusoidal inputs. For single-, dual-, multiple-sinusoidal and Gaussian inputs the error is less than 2 dB for the 5th-order and reduces to less than 1 dB for 6th- and higher-order Δ-Σ modulators

Nonlinear Stability Prediction of Multibit Delta-Sigma Modulators for Sinusoidal Inputs

This paper proposes a novel algorithm that can be integrated with various design and evaluation tools, to more accurately and rapidly predict stability in multi-bit delta-sigma (Δ-Σ) modulators. Analytical expressions using the nonlinear gains from the concept of modified nonlinearity in control theory are incorporated into the mathematical model of multi-bit Δ-Σ modulators to predict the stable amplitude limits for sinusoidal input signals. The nonlinear gains lead to a set of equations which can numerically estimate the quantizer gain as a function of the input sinusoidal signal amplitude. This method is shown to accurately predict the stable amplitude limits of sinusoids for 2nd-, 3rd-, 4th-, 5th- and 6th-order 3- and 5-level mid-tread quantizer based Δ-Σ modulators. The algorithm is simple to apply and can be extended to midrise quantizers or to any number of quantizer levels. The only required input parameters for this algorithm are the number of quantizer levels and the coefficients of the noise transfer function

Analysis, simulation and design of nonlinear RF circuits

The PhD project consists of two parts. The first part concerns the development of Computer Aided Design (CAD) algorithms for high-frequency circuits. Novel Padébased algorithms for numerical integration of ODEs as arise in high-frequency circuits are proposed. Both single- and multi-step methods are introduced. A large part of this section of the research is concerned with the application of Filon-type integration techniques to circuits subject to modulated signals. Such methods are tested with analog and digital modulated signals and are seen to be very effective. The results confirm that these methods are more accurate than the traditional trapezoidal rule and Runge-Kutta methods. The second part of the research is concerned with the analysis, simulation and design of RF circuits with emphasis on injection-locked frequency dividers (ILFD) and digital delta-sigma modulators (DDSM). Both of these circuits are employed in fractional-N frequency synthesizers. Several simulation methods are proposed to capture the locking range of an ILFD, such as the Warped Multi-time Partial Differential Equation (WaMPDE) and the Multiple-Phase-Condition Envelope Following (MPCENV) methods. The MPCENV method is the more efficient and accurate simulation technique and it is recommended to obviate the need for expensive experiments. The Multi-stAge noise Shaping (MASH) digital delta-sigma modulator (DDSM) is simulated in MATLAB and analysed mathematically. A novel structure employing multimoduli, termed the MM-MASH, is proposed. The goal in this design work is to reduce the noise level in the useful frequency band of the modulator. The success of the novel structure in achieving this aim is confirmed with simulations

Theory and applications of delta-sigma analogue-to-digital converters without negative feedback

Analog-to-digital converters play a crucial role in modern audio and communication design. Conventional Nyquist converters are suitable only for medium resolutions and require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can achieve high resolutions (>20bits) and can be implemented using straightforward, high-tolerance analog components. In conventional oversampled modulators, negative feedback is applied in order to control the dynamic behavior of a system and to realize the attenuation of the quantization noise in the signal band due to noise shaping. However, feedback can also introduce undesirable effects such as limit cycles, jitter problems in continuous-time topologies, and infinite impulse responses. Additionally, it increases the system complexity due to extra circuit components such as nonlinear multi-bit digital-to-analog converters in the feedback path. Moreover, in certain applications such as wireless, biomedical sensory, or microphone implementations feedback cannot be applied. As a result, the main goal of this thesis is to develop sigma-delta data converters without feedback. Various new delta-sigma analog-to-digital converter topologies are explored their mathematical models are presented. Simulations are carried out to validate these models and to show performance results. Specifically, two topologies, a first-order and a second-order oscillator-based delta-sigma modulator without feedback are described in detail. They both can be implemented utilizing VCOs and standard digital gates, thus requiring only few components. As proof of concept, two digital microphones based on these delta-sigma converters without feedback were implemented and experimental results are given. These results show adequate performance and provide a new approach of measuring

Simulation, and Overload and Stability Analysis of Continuous Time Sigma Delta Modulator

The ever increasing demand for faster and more powerful digital applications requires high speed, high resolution ADCs. Currently, sigma delta modulators ADCs are extensively used in broadband telecommunication systems because they are an effective solution for high data-rate wireless communication systems that require low power consumption, high speed, high resolution, and large signal bandwidths. Because mixed-signal integrated circuits such as Continuous Time sigma delta modulators contain both analog and digital circuits, mixed signal circuits are not as simple to model and simulate as all discrete or all analog systems. In this dissertation, the delta transform is used to simulate CT sigma delta modulators, and its speed and accuracy are compared to the other methods. The delta transform method is shown to be a very simple and effective method to get accurate results at reasonable speeds when compared with several existing simulation methods. When a CT sigma delta modulator is overloaded, sigma delta modulator\u27s output signal to quantization noise ratio (SQNR) decreases when the sigma delta modulator\u27s input is increased over a certain value. In this dissertation, the range of quantizer gains that cause overload are determined and the values ware used to determine the input signal power that prevents overload and the CT sigma delta modulator\u27s maximum SQNR. The CT sigma delta modulators from 2nd to 5th order are simulated to validate the predicted maximum input power that prevents overload and the maximum SQNR. Determining the stability criteria for CT sigma delta modulators is more difficult than it is for Discrete time sigma delta modulators (DT sigma delta modulators) because CT sigma delta modulators include delays which are modeled mathematically by exponential functions for CT systems. In this dissertation an analytical root locus method is used to determine the stability criteria for CT sigma delta modulators. This root locus method determines the range of quantizer gains for which a CT sigma delta modulator is stable. These values can then be used to determine input signal and internal signal powers that prevent sigma delta modulators from becoming unstable. Also, the maximum input power that keeps the CT sigma delta modulators stable for CT sigma delta modulators operating in overload can be determined. The CT sigma delta modulators from 2nd to 5th order are simulated to validate the predicted maximum input power that keeps the CT sigma delta modulators stable

Ultra-low Power Circuits and Architectures for Neuromorphic Computing Accelerators with Emerging TFETs and ReRAMs

Neuromorphic computing using post-CMOS technologies is gaining increasing popularity due to its promising potential to resolve the power constraints in Von-Neumann machine and its similarity to the operation of the real human brain. To design the ultra-low voltage and ultra-low power analog-to-digital converters (ADCs) for the neuromorphic computing systems, we explore advantages of tunnel field effect transistor (TFET) analog-to-digital converters (ADCs) on energy efficiency and temperature stability. A fully-differential SAR ADC is designed using 20 nm TFET technology with doubled input swing and controlled comparator input common-mode voltage. To further increase the resolution of the ADC, we design an energy efficient 12-bit noise shaping (NS) successive-approximation register (SAR) ADC. The 2nd-order noise shaping architecture with multiple feed-forward paths is adopted and analyzed to optimize system design parameters. By utilizing tunnel field effect transistors (TFETs), the Delta-Sigma SAR is realized under an ultra-low supply voltage VDD with high energy efficiency. The stochastic neuron is a key for event-based probabilistic neural networks. We propose a stochastic neuron using a metal-oxide resistive random-access memory (ReRAM). The ReRAM\u27s conducting filament with built-in stochasticity is used to mimic the neuron\u27s membrane capacitor, which temporally integrates input spikes. A capacitor-less neuron circuit is designed, laid out, and simulated. The output spiking train of the neuron obeys the Poisson distribution. Based on the ReRAM based neuron, we propose a scalable and reconfigurable architecture that exploits the ReRAM-based neurons for deep Spiking Neural Networks (SNNs). In prior publications, neurons were implemented using dedicated analog or digital circuits that are not area and energy efficient. In our work, for the first time, we address the scaling and power bottlenecks of neuromorphic architecture by utilizing a single one-transistor-one-ReRAM (1T1R) cell to emulate the neuron. We show that the ReRAM-based neurons can be integrated within the synaptic crossbar to build extremely dense Process Element (PE)–spiking neural network in memory array–with high throughput. We provide microarchitecture and circuit designs to enable the deep spiking neural network computing in memory with an insignificant area overhead