Smart Chips for Smart Surroundings -- 4S

The overall mission of the 4S project (Smart Chips for Smart Surroundings) was to define and develop efficient flexible, reconfigurable core building blocks, including the supporting tools, for future Ambient System Devices. Reconfigurability offers the needed flexibility and adaptability, it provides the efficiency needed for these systems, it enables systems that can adapt to rapidly changing environmental conditions, it enables communication over heterogeneous wireless networks, and it reduces risks: reconfigurable systems can adapt to standards that may vary from place to place or standards that have changed during and after product development. In 4S we focused on heterogeneous building blocks such as analogue, hardwired functions, fine and coarse grain reconfigurable tiles and microprocessors. Such a platform can adapt to a wide application space without the need for specialized ASICs. A novel power aware design flow and runtime system was developed. The runtime system decides dynamically about the near-optimal application mapping to the given hardware platform. The overall concept was verified on hardware platforms based on an existing SoC and in a second step with novel silicon. DRM (Digital Radio Mondiale) and MPEG4 Video applications have been implemented on the platforms demonstrating the adaptability of the 4S concept

Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems

International audience—Modern FPGAs provide great computational power and flexibility but there is still room for improving their performances. For example multiuser approaches are particularly underdeveloped as they require specific mechanisms still to be automated. Sharing an FPGA resource between applications or users requires a context switch ability. The latter enables pausing and resuming applications at system demand. This paper presents a method that automatically selects a good execution point, called hardware checkpoint, to perform a context switch on an FPGA. The method relies on a static analysis of the finite state machine of a circuit to select the checkpoint states. The obtained selection ensures that the context switch mechanism respects a given latency and tries to minimize the mechanism costs. The method takes advantage of its integration in an open-source HLS tool and preliminary results highlight its efficiency. Index Terms—FPGA, HLS, CAD, hardware context switc

Final report on dissemination, regulation, standardization, exploitation & training : D6.3

In D6.1 deliverable project dissemination, exploitation and training plans, as well as standardization & regulatory approach strategy was presented. The D6.2 reported on the necessary updates of these strategies and the actions taken by the partners in line with them, as well as the obtained results. In this D6.3 deliverable, a full set of project dissemination activities, standardization & regulatory contributions as well as an operator’s “cook book” outlining steps necessary for full deployment of ON functionality and services, are presented.Deliverable D6.3 del projecte OneFITPostprint (author’s final draft

The State-of-the-Art and Prospects of Learning Factories

AbstractChangeability of manufacturing systems is an important enabler for offering large variety of competitive products to satisfy customers’ requirements. Learning factories, as teaching and research environments, can play a key role in developing new solutions for changeability, transferring them to the industry and using them in educating engineers. The results of a survey of existing learning factories and their characteristics are presented. Their use in research, teaching and industrial projects is analyzed. A novel scheme to classify those systems with regard to their design, products and their changeability characteristics is outlined. Conclusions about the future of learning factories are drawn

Coarse-grained reconfigurable array architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code