Implementation of Banker’s Algorithm Using Dynamic Modified Approach

Banker’s algorithm referred to as resource allocation and deadlock avoidance algorithm that checks for the safety by simulating the allocation of predetermined maximum possible of resources and makes the system into s-state by checking the possible deadlock conditions for all other pending processes. It needs to know how much of each resource a process could possibly request. Number of processes are static in algorithm, but in most of system processes varies dynamically and no additional process will be started while it is in execution. The number of resources are not allow to go down while it is in execution. In this research an approach for Dynamic Banker's algorithm is proposed which allows the number of resources to be changed at runtime that prevents the system to fall in unsafe state. It also give details about all the resources and processes that which one require resources and in what quantity. This also allocates the resource automatically to the stopped process for the execution and will always give the appropriate safe sequence for the given processes

A Dynamic and Improved Implementation of Banker’s Algorithm

Banker’s algorithm can be described as deadlock avoidance and resource allocation algorithm which ensure the execution safety by simulating the allocation of already determined maximum possible of resources and makes the system into s-state by checking the possible deadlock conditions for all other pending processes. It needs to know how much of each resource a process could possibly request. Number of processes is static in algorithm, but in most of system processes varies dynamically and no additional process will be started while it is in execution. The number of resources is not allowed to go down while it is in execution. In this research an approach for Dynamic Banker's algorithm is proposed which allows the number of resources to be changed at runtime that prevents the system to fall in unsafe state. It also gives details about all the resources and processes that which one requires resources and in what quantity. This modified banker’s algorithm performs the process arrangement on the basis of their needs that leads to solve the problem in less time

A flexible simulaton framework for the study of deadlock resolution algorithms in multicore systems

Deadlock is a common phenomenon in software applications, yet it is ignored by most operating systems. Although the occurrence of a deadlocks in systems is not frequent, in some cases, the effects are drastic when deadlock occurs. The ongoing trend in processor technology indicates that future systems will have hundreds and thousands of cores. Due to this imminent trend in hardware development, the problem of deadlock has gained renewed attention in research. Deadlock handling techniques that are developed for earlier processors and distributed systems might not work well with multicore systems, due to their architectural differences. Hence, to maximize the utility of multicore systems, new programs have to be carefully designed and tested before they can be adopted for practical use. Many approaches have been developed to handle deadlock in multicore systems, but very little attention has been paid to comparing the performance of those approaches with respect to different performance parameters. To fulfil the above mentioned shortfalls, we need a flexible simulation testbed to study deadlock handling algorithms and to observe their performance differences in multicore systems. The development of such a framework is the main goal of this thesis. In the framework, we implemented a general a scenario, scenario for the Dining Philosopher's problem and scenario for the Banker's algorithm. In addition to these scenarios, we demonstrate the flexibility, soundness, and use of the proposed framework by simulating two different deadlock handling strategies "" deadlock avoidance (the Banker's algorithm) and deadlock detection (Dreadlocks). The deadlock detection is followed by deadlock recovery to resolve the detected deadlock. We also present result analysis for the different set of experiments performed on the implemented strategies. The proposed simulation testbed to study deadlocks in multicore systems is developed using Java. --Leaf i.The original print copy of this thesis may be available here: http://wizard.unbc.ca/record=b214097

Deadlock avoidance with virtual channels

High Performance Computing is a rapidly evolving area of computer science which attends to solve complicated computational problems with the combination of computational nodes connected through high speed networks. This work concentrates on the networks problems that appear in such networks and specially focuses on the Deadlock problem that can decrease the efficiency of the communication or even destroy the balance and paralyze the network. Goal of this work is the Deadlock avoidance with the use of virtual channels, in the switches of the network where the problem appears. The deadlock avoidance assures that will not be loss of data inside network, having as result the increased latency of the served packets, due to the extra calculation that the switches have to make to apply the policy.La computación de alto rendimiento es una zona de rápida evolución de la informática que busca resolver complicados problemas de cálculo con la combinación de los nodos de cómputo conectados a través de redes de alta velocidad. Este trabajo se centra en los problemas de las redes que aparecen en este tipo de sistemas y especialmente se centra en el problema del "deadlock" que puede disminuir la eficacia de la comunicación con la paralización de la red. El objetivo de este trabajo es la evitación de deadlock con el uso de canales virtuales, en los conmutadores de la red donde aparece el problema. Evitar el deadlock asegura que no se producirá la pérdida de datos en red, teniendo como resultado el aumento de la latencia de los paquetes, debido al overhead extra de cálculo que los conmutadores tienen que hacer para aplicar la política.La computació d'alt rendiment és una àrea de ràpida evolució de la informàtica que pretén resoldre complicats problemes de càlcul amb la combinació de nodes de còmput connectats a través de xarxes d'alta velocitat. Aquest treball se centra en els problemes de les xarxes que apareixen en aquest tipus de sistemes i especialment se centra en el problema del "deadlock" que pot disminuir l'eficàcia de la comunicació amb la paralització de la xarxa. L'objectiu d'aquest treball és l'evitació de deadlock amb l'ús de canals virtuals, en els commutadors de la xarxa on apareix el problema. Evitar deadlock assegura que no es produirà la pèrdua de dades en xarxa, tenint com a resultat l'augment de la latència dels paquets, degut al overhead extra de càlcul que els commutadors han de fer per aplicar la política

Data routing in multicore processors using dimension increment method

A Deadlock-free routing algorithm can be generated for arbitrary interconnection network using the concept of virtual channels but the virtual channels will lead to more complex algorithms and more demands of NOC resource. In this thesis, we study a Torus topology for NOC application, design its structure and propose a routing algorithm exploiting the characteristics of NOC. We have chosen a typical 16 (4 by 4) routers Torus and propose the corresponding route algorithm. In our algorithm, all the channels are assigned 4 different dimensions (n0,n1,n2 & n3). By following the dimension increment method, we break the dependent route circles, and avoid dead lock and live-lock and avoid the overhead of virtual channels. Xilinx offers two soft core processors, namely Picoblaze and Microblaze. The Picoblaze processor is 8-bit configurable processor core. These soft processor cores offer designers tremendous flexibility during the design process, allowing the designers to configure the processor to meet the needs of their systems (e.g., adding custom instructions or including/excluding particular data path coprocessors) and to quickly integrate the processor within any FPGA. Unlike single chip Microprocessor/FPGA systems using hard-core processors, soft processor cores allow designers to incorporate varying numbers of processors within a single FPGA design depending on an application’s needs.Soft processor cores implemented using FPGAs typically have higher power consumption and decreased performance compared with hard-core processors. Key features of the Picoblaze processor, as well as other soft processor cores, include the user configurable options that allow a designer to tailor the processor’s functionality to their specific design. The proposed design implements sixteen instances of a soft processor, Picoblaze, connected in a torus topology. Data is passed from one processor to another employing a routing algorithm which is based on dimension increment method. Thus we design an NOC with multiple microcontrollers and related logic, synthesize the process and test its performance in a simulation environment

Simulation in Automated Guided Vehicle System Design

The intense global competition that manufacturing companies face today results in an increase of product variety and shorter product life cycles. One response to this threat is agile manufacturing concepts. This requires materials handling systems that are agile and capable of reconfiguration. As competition in the world marketplace becomes increasingly customer-driven, manufacturing environments must be highly reconfigurable and responsive to accommodate product and process changes, with rigid, static automation systems giving way to more flexible types. Automated Guided Vehicle Systems (AGVS) have such capabilities and AGV functionality has been developed to improve flexibility and diminish the traditional disadvantages of AGV-systems. The AGV-system design is however a multi-faceted problem with a large number of design factors of which many are correlating and interdependent. Available methods and techniques exhibit problems in supporting the whole design process. A research review of the work reported on AGVS development in combination with simulation revealed that of 39 papers only four were industrially related. Most work was on the conceptual design phase, but little has been reported on the detailed simulation of AGVS. Semi-autonomous vehicles (SA V) are an innovative concept to overcome the problems of inflexible -systems and to improve materials handling functionality. The SA V concept introduces a higher degree of autonomy in industrial AGV -systems with the man-in-the-Ioop. The introduction of autonomy in industrial applications is approached by explicitly controlling the level of autonomy at different occasions. The SA V s are easy to program and easily reconfigurable regarding navigation systems and material handling equipment. Novel approaches to materials handling like the SA V -concept place new requirements on the AGVS development and the use of simulation as a part of the process. Traditional AGV -system simulation approaches do not fully meet these requirements and the improved functionality of AGVs is not used to its full power. There is a considerflble potential in shortening the AGV -system design-cycle, and thus the manufacturing system design-cycle, and still achieve more accurate solutions well suited for MRS tasks. Recent developments in simulation tools for manufacturing have improved production engineering development and the tools are being adopted more widely in industry. For the development of AGV -systems this has not fully been exploited. Previous research has focused on the conceptual part of the design process and many simulation approaches to AGV -system design lack in validity. In this thesis a methodology is proposed for the structured development of AGV -systems using simulation. Elements of this methodology address the development of novel functionality. The objective of the first research case of this research study was to identify factors for industrial AGV -system simulation. The second research case focuses on simulation in the design of Semi-autonomous vehicles, and the third case evaluates a simulation based design framework. This research study has advanced development by offering a framework for developing testing and evaluating AGV -systems, based on concurrent development using a virtual environment. The ability to exploit unique or novel features of AGVs based on a virtual environment improves the potential of AGV-systems considerably.University of Skovde. European Commission for funding the INCO/COPERNICUS Projec

A pattern-based development of secure business processes

Iga andmeturbest huvitatud äriettevõte valib iseendale sobilikud turvameetmed, et vältida ootamatuid sündmusi ja õnnetusi. Nende turvameetmete esmane ülesanne on kaitsta selle äriettevõtte ressursse ja varasid. Äriettevõtetes aset leidvad õnnetused (vähemtähtsad või katastroofilised) on enamikel juhtudel oma olemuselt sarnased ning põhjustatud sarnaste turvariskide poolt. Paljudel andmeturbe spetsialistidel on raskusi leidmaks õiget lahendust konkreetsetele probleemidele, kuna eelmiste samalaadsete probleemide lahendused ei ole korrektselt dokumenteeritud. Selles kontekstis on turvalisuse mustrid (Security Patterns) kasulikud, kuna nad esitavad tõestatud lahendusi spetsiifiliste probleemide jaoks. Käesolevas väitekirjas arendasime välja kümme turvariskidele suunatud mustrit (SRP ehk Security Risk-oriented Patterns) ja defineerisime, kuidas kasutada neid mustreid vastumeetmetena turvariskidele äriprotsesside mudelite sees. Oma olemuselt on need mustrid sõltumatud modelleerimiskeelest. Lihtsustamaks nende rakendamist, on mudelid esitatud graafilises vormingus äriprotsesside modelleerimise keeles (BPMN). Me demonstreerime turvariskidele suunatud mustrite (SRP) kasutatavust kahe tööstusettevõtte ärimudeli näite põhjal. Esitame mustrite rakendamise kohta kvantitatiivsed analüüsid ja näitame, kuidas turvariskidele suunatud mustrid (SRP) aitavad demonstreerida andmeturbe nõrku kohti ärimudelites ning pakume välja lahendusi andmeturvalisusega seotud probleemidele. Selle uurimistöö tulemused võivad julgustada andmeturvalisusega tegelevaid analüütikuid jälgima mustritel-põhinevaid lähenemisi oma äriettevõtete kaitsmiseks, et aidata seeläbi kaasa ka infosüsteemide (Information Systems (IS)) kaitsmisele.Every security concerned enterprise selects its own security measures in order to avoid unexpected events and accidents. The main objective of these security measures is to protect the enterprise’s own resources and assets from damage. Most of the time, the accidents or disasters take place in enterprise are similar in nature, and are caused by similar kind of vulnerabilities. However, many security analysts find it difficult to select the right security measure for a particular problem because the previous proven solutions are not properly documented. In this context Security Patterns could be helpful since they present the proven solutions that potentially could be reused in the similar situations. In this thesis, we develop a set of ten Security Risk-oriented Patterns (SRP) and define the way how they could be used to define security countermeasures within the business process models. In principle, patterns are modelling language-independent. Moreover, to ease their application, we represent them in a graphical form using the Business Process Modelling Notation (BPMN) modelling approach. We demonstrate the usability of the Security Risk-oriented Patterns (SRP) by applying them on two industrial business models. We present the quantitative analysis of their application. We show that Security Risk-oriented Patterns (SRP) help to determine security risks in business models and suggest rationale for security solutions. The results of this research could potentially encourage the security analysts to follow pattern-based approach to develop secure business processes, thus, contributing to secure Information Systems (IS)

Process Synchronization in Computer Networks

Synchronization is used in real life so as to organize the work to grantee its continuation and preventing what we call blocking, which means no one go on working. Synchronization has a technical meaning in computer field that is related to this meaning but somewhat different. However, synchronization is increasingly used and being an important issue with the development of operating systems which improve the possibility for processes to cooperate with each other even in distributed systems. Processes can operate within one machine using shared memory or through multiple machines using message passing. This thesis searches how to achieve process synchronization either on a single machine or multicomputer systems. In the former one, synchronization can be achieved using multiple methods such as semaphore and monitor, where as in the later one we can use centralized, distributed or token ring algorithms. Then we focus on one of synchronization problems, deadlock. Deadlock is a situation where two or more processes are all blocked and none of them can become unblocked until one of others become unblocked. Three methods for handling deadlock situation: prevention avoidance, and detection. A C++ program has been designed using Message-Passing Interface (MPI) under LINUX operating system to execute a producer – consumer synchronization problem

Metaheuristic-based dispatching optimization integrated in multi-scale simulation model of railway operation

The dispatching system serves as an integral component of railway operation control and aims to eliminate the negative impacts of unforeseen events occurred during the operation process. On account of the time-critical decision-making and the associated complexity of the process-integrated dispatching, an acceptable compromise must be found regularly between the processing time of a dispatching task, which is often determined by the computer technology, and the dispatching solution quality. This applies equally to simulation software of railway operation, in order to make the workload of operational investigations acceptable. Accordingly, it is particularly important in the design of dispatching tools to find a good balance between required computation time and sufficient quality of results. With this central goal, a dispatching optimization algorithm was developed in this dissertation, which is based on a widely used metaheuristic algorithm - tabu search - and the integration in a multi-scale simulation model. The approach is based directly on the findings from the DFG project “The influence of dispatching on the relationship between capacity and operation quality of railway systems” and expands these by a universal multi-scale model. The multi-scale simulation model is characterized by continuously scaling, in which railway operation processes are simulated on microscopic, mesoscopic and macro-scopic levels concurrently. For large investigation areas, the relevant areas are pre-sented on microscopic level, while the others are presented on more efficient mesoscopic and macroscopic levels. Furthermore, an assessment method for the multi-scale model was developed to determine the significant values of different in-frastructure elements in the investigation area. Depending on the significant values, the simulation model can migrate continuously between three abstraction levels, so that the computational complexity and the accuracy of simulation results are well-balanced. With the proposed multi-scale simulation model, the sequence of train movements can be determined by the simplest dispatching principle (First Come First Serve) or a predefined dispatching solution. “First Come First Serve” is employed to generate basic dispatching solutions, while predefined dispatching solutions are used to simulate and evaluate optimized solutions. The simulation model-supported tabu search-based algorithm for dispatching optimization is able to optimize the basic solution by a series of dispatching measures iteratively until a satisfactory solution is obtained. It could be proved by means of a reference example that the developed algorithm for dispatching optimization can provide a suboptimal/optimal solution in a limited time