Investigation of ultra-thin Al₂O₃ film as Cu diffusion barrier on low-k (k=2.5) dielectrics

Ultrathin Al(2)O(3) films were deposited by PEALD as Cu diffusion barrier on low-k (k=2.5) material. The thermal stability and electrical properties of the Cu/low k system with Al(2)O(3) layers with different thickness were studied after annealing. The AES, TEM and EDX results revealed that the ultrathin Al(2)O(3) films are thermally stable and have excellent Cu diffusion barrier performance. The electrical measurements of dielectric breakdown and TDDB tests further confirmed that the ultrathin Al(2)O(3) film is a potential Cu diffusion barrier in the Cu/low-k interconnects system

Noncontact electrical metrology of Cu/low-k interconnect for semiconductor production wafers

We have demonstrated a technique capable of in-line measurement of dielectric constant of low-k interconnect films on patterned wafers utilizing a test key of ~50x50 \mu m in size. The test key consists of a low-k film backed by a Cu grid with >50% metal pattern density and <250 nm pitch, which is fully compatible with the existing dual-damascene interconnect manufacturing processes. The technique is based on a near-field scanned microwave probe and is noncontact, noninvasive, and requires no electrical contact to or grounding of the wafer under test. It yields <0.3% precision and 2% accuracy for the film dielectric constant

Dynamic Finite Element Analysis on Underlay Microstructure of Cu/low-k Wafer during Wirebonding

The aim of present research is to investigate dynamic stress analysis for microstructure of Cu/Low-K wafer subjected to wirebonding predicted by finite element software ANSYS/LS-DYNA. Two major analyses are conducted in the present research. In the first, the characteristic of heat affected zone (HAZ) and free air ball (FAB) on ultra thin Au wire have been carefully experimental measured. Secondary, the dynamic response on Al pad/beneath the pad of Cu/low-K wafer during wirebonding process has been successfully predicted by finite element analysis (FEA). Tensile mechanical properties of ultra thin wire before/after electric flame-off (EFO) process have been investigated by self-design pull test fixture. The experimental obtained hardening value has significantly influence on localize stressed area on Al pad. This would result in Al pad squeezing around the smashed FAB during impact stage and the consequent thermosonic vibration stage. Microstructure of FAB and HAZ are also carefully measured by micro/nano indentation instruments. All the measured data serves as material inputs for the FEA explicit software ANSYS/LS-DYNA. Because the crack of low-k layer and delamination of copper via are observed, dynamic transient analysis is performed to inspect the overall stress/strain distributions on the microstructure of Cu/low-k wafer. Special emphasizes are focused on the copper via layout and optimal design of Cu/low-k microstructure. It is also shown that the Al pad can be replaced by Al-Cu alloy pad or Cu pad to avoid large deformation on pad and cracking beneath the surface. A series of comprehensive experimental works and FEA predictions have been performed to increase bondability and reliability in this study

Scaling and process effect on electromigration reliability for Cu/low k interconnects

textThe microelectronics industry has been managing the RC delay problem arising from aggressive line scaling, by replacing aluminum (Al) by copper (Cu) and oxide dielectric by low-k dielectric. Electromigration (EM) turned out to be a serious reliability problem for Cu interconnects due to the implementation of mechanically weaker low-k dielectrics. In addition, line width and via size scaling resulted in the need of a novel diffusion barrier, which should be uniform and thin. The objective of this dissertation is to investigate the impacts of Ta barrier process, such as barrier-first and pre-clean first, and scaling of barrier and line/via on EM reliability of Cu/low-k interconnects. For this purpose, EM statistical test structures, having different number of line segments, line width, and via width, were designed. The EM test structures were fabricated by a dualdamascene process with two metal layers (M1/Via/M2), which were then packaged for EM tests. The package-level EM tests were performed in a specially designed vacuum chamber with pure nitrogen environment. The novel barrier deposition process, called barrier-first, showed a higher (jL)[subscript c] product and prolonged EM lifetime, compared with the conventional Ta barrier deposition process, known as pre-clean first. This can be attributed to the improved uniformity and thickness of the Ta layer on the via and trench, as confirmed by TEM. As for the barrier thickness effect, the (jL)c product decreased with decreasing thickness, due to reduced Cu confinement. A direct correlation between via size and EM reliability was found; namely, EM lifetime and statistics degraded with via size. This can be attributed to the fact that critical void length to cause open circuit is about the size of via width. To investigate further line scaling effect on EM reliability, SiON (siliconoxynitride) trenchfilling process was introduced to fabricate 60-nm lines, corresponding to 45-nm technology, using a conventional, wider line lithograph technology. The EM lifetime of 60-nm fine lines with SiON filling was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via/metal-1 interface.Materials Science and Engineerin

Near-field scanning microwave microscope for interline capacitance characterization of nanoelectronics interconnect

We have developed a noncontact method for measurement of the interline capacitance in Cu/low-k interconnect. It is based on a miniature test vehicle with net capacitance of a few femto-Farads formed by two 20-\mu m-long parallel wires (lines) with widths and spacings the same as those of the interconnect wires of interest. Each line is connected to a small test pad. The vehicle impedance is measured at 4 GHz by a near-field microwave probe with 10 \mu m probe size via capacitive coupling of the probe to the vehicle's test pads. Full 3D finite element modeling at 4 GHz confirms that the microwave radiation is concentrated between the two wires forming the vehicle. An analytical lumped element model and a short/open calibration approach have been proposed to extract the interline capacitance value from the measured data. We have validated the technique on several test vehicles made with copper and low-k dielectric on a 300 mm wafer. The vehicles interline spacing ranges from 0.09 to 1 \mu m and a copper line width is 0.15 \mu m. This is the first time a near-field scanning microwave microscope has been applied to measure the lumped element impedance of a test vehicle

Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

Master'sMASTER OF ENGINEERIN

Effects of mechanical properties on the reliability of Cu/low-k metallization systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (leaves 211-217).Cu and low-dielectric-constant (k) metallization schemes are critical for improved performance of integrated circuits. However, low elastic moduli, a characteristic of the low-k materials, lead to significant reliability degradation in Cu-interconnects. A thorough understanding of the effects of mechanical properties on electromigration induced failures is required for accurate reliability assessments. During electromigration inside Cu-interconnects, a change in atomic concentration correlates with a change in stress through the effective bulk modulus of the materials system, B, which decreases as the moduli of low-k materials used as inter-level dielectrics (ILDs) decrease. This property is at the core of discussions on electromigration-induced failures by all mechanisms. B is computed using finite element modeling analyses, using experimentally determined mechanical properties of the individual constituents. Characterization techniques include nanoindentation, cantilever deflection, and pressurized membrane deflection for elastic properties measurements, and chevron-notched double-cantilever pull structures for adhesion measurements. The dominant diffusion path in Cu-interconnects is the interface between Cu and the capping layer, which is currently a Si3N4-based film. We performed experiments on Cu-interconnect segments to investigate the kinetics of electromigration. A steady resistance increase over time prior to open-circuit failure, a result of void growth, correlates with the electromigration drift velocity. Diffusive measurements made in this fashion are more fundamental than lifetime measurements alone, and correlate with the combined effects of the electron wind and the back stress forces during electromigration induced void growth.(cont.)Using this method, the electromigration activation energy was determined to be 0.80±0.06eV. We conducted experiments using Cu-interconnects with different lengths to study line length effects. Although a reliability improvement is observed as the segment length decreases, there is no deterministic current-density line-length product, jL, for which all segments are immortal. This is because small, slit-like voids forming directly below vias will cause open-failures in Cu-interconnects. Therefore, the probabilistic jLcrit values obtained from via-above type nterconnects approximate the thresholds for void nucleation. The fact that jLcrit,nuc monotonically decreases with B results from an energy balance between the strain energy released and surface energy cost for void nucleation and the critical stress required for void nucleation is proportional to B. We also performed electromigration experiments using Cu/low-k interconnect trees to investigate the effects of active atomic sinks and reservoirs on interconnect reliability. In all cases, failures were due to void growth. Kinetic parameters were extracted to be ... Quantitative analysis demonstrates that the reliability of the failing segments is modulated by the evolution of stress in the whole interconnect tree. During this process, not only the diffusive parameters but also B play critical roles. However, as B decreases, the positive effects of reservoirs on reliability are diminished, while the negative effects of sinks on reliability are amplified.(cont.) Through comprehensive failure analyses, we also successfully identified the mechanism of electromigration-induced extrusions in Cu/low-k interconnects to be nearmode-I interfacial fracture between the Si3N4-based capping layer and the metallization/ILD layer below. The critical stress required for extrusion is found to depend not only on B but also on the layout and dimensions of the interconnects. As B decreases, sparsely packed, wide interconnects are most prone to extrusion-induced failures. Altogether, this research accounts for the effects of mechanical properties on all mechanisms of failure due to electromigration. The results provide an improved experimental basis for accurate circuit-level, layout-specific reliability assessments.by Frank LiLi Wei.Ph.D

Stress modeling of multi level interconnect schemes for future deep submicron device generations

Copper and low dielctric constantant (k) materials are poised to become the dominant interconnect scheme for integrated circuits for the future because of the low resistance and capacitance that they offer which can improve circuit performance by more than 30% over conventional interconnect schemes. This paper addresses the thermomechanical stresses in the Cu/Low k interconnect scheme through numerical simulation and identifies the locations of maximum stress in the structure with view to providing information on the impact that different dielectric materials have on the stress distribution in the interfaces between metals and dielectric layers

Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness

In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates