39 research outputs found
Network-on-Chip
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems
Design of complex integrated systems based on networks-on-chip: Trading off performance, power and reliability
The steady advancement of microelectronics is associated with an escalating number of challenges for design engineers due to both the tiny dimensions and the enormous complexity of integrated systems. Against this background, this work deals with Network-On-Chip (NOC) as the emerging design paradigm to cope with diverse issues of nanotechnology. The detailed investigations within the chapters focus on the communication-centric aspects of multi-core-systems, whereas performance, power consumption as well as reliability are considered likewise as the essential design criteria
Doctor of Philosophy
dissertationCommunication surpasses computation as the power and performance bottleneck in forthcoming exascale processors. Scaling has made transistors cheap, but on-chip wires have grown more expensive, both in terms of latency as well as energy. Therefore, the need for low energy, high performance interconnects is highly pronounced, especially for long distance communication. In this work, we examine two aspects of the global signaling problem. The first part of the thesis focuses on a high bandwidth asynchronous signaling protocol for long distance communication. Asynchrony among intellectual property (IP) cores on a chip has become necessary in a System on Chip (SoC) environment. Traditional asynchronous handshaking protocol suffers from loss of throughput due to the added latency of sending the acknowledge signal back to the sender. We demonstrate a method that supports end-to-end communication across links with arbitrarily large latency, without limiting the bandwidth, so long as line variation can be reliably controlled. We also evaluate the energy and latency improvements as a result of the design choices made available by this protocol. The use of transmission lines as a physical interconnect medium shows promise for deep submicron technologies. In our evaluations, we notice a lower energy footprint, as well as vastly reduced wire latency for transmission line interconnects. We approach this problem from two sides. Using field solvers, we investigate the physical design choices to determine the optimal way to implement these lines for a given back-end-of-line (BEOL) stack. We also approach the problem from a system designer's viewpoint, looking at ways to optimize the lines for different performance targets. This work analyzes the advantages and pitfalls of implementing asynchronous channel protocols for communication over long distances. Finally, the innovations resulting from this work are applied to a network-on-chip design example and the resulting power-performance benefits are reported
On Energy Efficient Computing Platforms
In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms.
As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects.
As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency.
With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption.
Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.Siirretty Doriast
Physical Design and Clock Tree Synthesis Methods For A 8-Bit Processor
Now days a number of processors are available with a lot kind of feature from different industries. A processor with similar kind of architecture of the current processors only missing the memory stuffs like the RAM and ROM has been designed here with the help of Verilog style of coding. This processor contains architecturally the program counter, instruction register, ALU, ALU latch, General Purpose Registers, control state module, flag registers and the core module containing all the modules. And a test module is designed for testing the processor. After the design of the processor with successful functionality, the processor is synthesized with 180nm technology. The synthesis is performed with the data path optimization like the selection of proper adders and multipliers for timing optimization in the data path while the ALU operations are performed. During synthesis how to take care of the worst negative slack (WNS), how to include the clock gating cells, how to define the cost and path groups etc. have been covered. After the proper synthesis we get the proper net list and the synthesized constraint file for carrying out the physical design. In physical design the steps like floor-planning, partitioning, placement, legalization of the placement, clock tree synthesis, and routing etc. have been performed. At all the stages the static timing analysis is performed for the timing meet of the design for better performance in terms of timing or frequency. Each steps of physical design are discussed with special effort towards the concepts behind the step. Out of all the steps of physical design the clock tree synthesis is performed with some improvement in the performance of the clock tree by creating a symmetrical clock tree and maintaining more common clock paths. A special algorithm has been framed for creating a symmetrical clock tree and thereby making the power consumption of the clock tree low
Advanced modelling and design considerations for interconnects in ultra- low power digital system
PhD ThesisAs Very Large Scale Integration (VLSI) is progressing in very Deep
submicron (DSM) regime without decreasing chip area, the importance
of global interconnects increases but at the cost of
performance and power consumption for advanced System-on-
Chip (SoC)s. However, the growing complexity of interconnects
behaviour presents a challenge for their adequate modelling,
whereby conventional circuit theoretic approaches cannot provide
sufficient accuracy. During the last decades, fractional differential
calculus has been successfully applied to modelling
certain classes of dynamical systems while keeping complexity
of the models under acceptable bounds. For example, fractional
calculus can help capturing inherent physical effects in electrical
networks in a compact form, without following conventional
assumptions about linearization of non-linear interconnect components.
This thesis tackles the problem of interconnect modelling in
its generality to simulate a wide range of interconnection configurations,
its capacity to emulate irregular circuit elements
and its simplicity in the form of responsible approximation. This
includes modelling and analysing interconnections considering
their irregular components to add more flexibility and freedom
for design. The aim is to achieve the simplest adaptable model
with the highest possible accuracy. Thus, the proposed model
can be used for fast computer simulation of interconnection
behaviour. In addition, this thesis proposes a low power circuit
for driving a global interconnect at voltages close to the noise
level. As a result, the proposed circuit demonstrates a promising
solution to address the energy and performance issues related
to scaling effects on interconnects along with soft errors that
can be caused by neutron particles.
The major contributions of this thesis are twofold. Firstly, in
order to address Ultra-Low Power (ULP) design limitations, a novel
driver scheme has been configured. This scheme uses a bootstrap
circuitry which boosts the driver’s ability to drive a long
interconnect with an important feedback feature in it. Hence,
this approach achieves two objectives: improving performance
and mitigating power consumption. Those achievements are essential
in designing ULP circuits along with occupying a smaller
footprint and being immune to noise, observed in this design as
well. These have been verified by comparing the proposed design
to the previous and traditional circuits using a simulation tool.
Additionally, the boosting based approach has been shown beneficial
in mitigating the effects of single event upset (SEU)s, which
are known to affect DSM circuits working under low voltages.
Secondly, the CMOS circuit driving a distributed RLC load has
been brought in its analysis into the fractional order domain. This
model will make the on-chip interconnect structure easy to adjust
by including the effect of fractional orders on the interconnect
timing, which has not been considered before. A second-order
model for the transfer functions of the proposed general structure
is derived, keeping the complexity associated with second-order
models for this class of circuits at a minimum. The approach
here attaches an important trait of robustness to the circuit
design procedure; namely, by simply adjusting the fractional
order we can avoid modifying the circuit components. This can
also be used to optimise the estimation of the system’s delay
for a broad range of frequencies, particularly at the beginning
of the design flow, when computational speed is of paramount
importance.Iraqi Ministry of Higher Education
and Scientific Researc
Energy-precision tradeoffs in the graphics pipeline
The energy consumption of a graphics processing unit (GPU) is an important factor in its design, whether for a server, desktop, or mobile device. Mobile products, such as smart phones, tablets, and laptop computers, rely on batteries to function; the less the demand for power is on these batteries, the longer they will last before needing to be recharged. GPUs used in servers and desktops, while not dependent on a battery for operation, are still limited by the efficiency of power supplies and heat dissipation techniques. In this dissertation, I propose to lower the energy consumption of GPUs by reducing the precision of floating-point arithmetic in the graphics pipeline and the data sent and stored on- and off-chip. The key idea behind this work is twofold: energy can be saved through a systematic and targeted reduction in the number of bits 1) computed and 2) communicated. Reducing the number of bits computed will necessarily reduce either the precision or range of a floating point number. I focus on saving energy by way of reducing precision, which can exploit the over-provisioning of bits in many stages of the graphics pipeline. Reducing the number of bits communicated takes several forms. First, I propose enhancements to existing compression schemes for off-chip buffers to save bandwidth. I also suggest a simple extension that exploits unused bits in reduced-precision data undergoing compression. Finally, I present techniques for saving energy in on-chip communication of reduced-precision data. By designing and simulating variable-precision arithmetic circuits with promising energy versus precision characteristics and tradeoffs, I have developed an energy model for GPUs. Using this model and my techniques, I have shown that significant savings (up to 70% in computation in the vertex and pixel shader stages) are possible by reducing the precision of the arithmetic. Further, my compression approaches have enabled improvements of 1.26x over past work, and a general-purpose compressor design has achieved bandwidth savings of 34%, 87%, and 65% for color, depth, and geometry data, respectively, which is competitive with past work. Lastly, an initial exploration in signal gating unused lines in on-chip buses has suggested savings of 13-48% for the tested applications' traffic from a multiprocessor's register file to its L1 cache
VLSI Design
This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc
Practical free-space quantum key distribution
Within the last two decades, the world has seen an exponential increase in the quantity
of data traffic exchanged electronically. Currently, the widespread use of classical
encryption technology provides tolerable levels of security for data in day to day life.
However, with one somewhat impractical exception these technologies are based on
mathematical complexity and have never been proven to be secure. Significant advances
in mathematics or new computer architectures could render these technologies obsolete
in a very short timescale.
By contrast, Quantum Key Distribution (or Quantum Cryptography as it is sometimes
called) offers a theoretically secure method of cryptographic key generation and
exchange which is guaranteed by physical laws. Moreover, the technique is capable of
eavesdropper detection during the key exchange process. Much research and
development work has been undertaken but most of this work has concentrated on the
use of optical fibres as the transmission medium for the quantum channel. This thesis
discusses the requirements, theoretical basis and practical development of a compact,
free-space transmission quantum key distribution system from inception to system tests.
Experiments conducted over several distances are outlined which verify the feasibility
of quantum key distribution operating continuously over ranges from metres to intercity distances and finally to global reach via the use of satellites