9 research outputs found
Fast Algorithm Designs of Multiple-Mode Discrete Integer Transforms with Cost-Effective and Hardware-Sharing Architectures for Multistandard Video Coding Applications
In this chapter, first we give a brief view of transform-based video coding. Second, the basic matrix decomposition scheme for fast algorithm and hardware-sharing-based integer transform design are described. Finally, two case studies for fast algorithm and hardware-sharing-based architecture designs of discrete integer transforms are presented, where one is for the single-standard multiple-mode video transform-coding application, and the other is for the multiple-standard multiple-mode video transform-coding application
Algoritmo de estimação de movimento e sua arquitetura de hardware para HEVC
Doutoramento em Engenharia EletrotécnicaVideo coding has been used in applications like video surveillance, video
conferencing, video streaming, video broadcasting and video storage. In a
typical video coding standard, many algorithms are combined to compress a
video. However, one of those algorithms, the motion estimation is the most
complex task. Hence, it is necessary to implement this task in real time by
using appropriate VLSI architectures. This thesis proposes a new fast motion
estimation algorithm and its implementation in real time. The results show that
the proposed algorithm and its motion estimation hardware architecture out
performs the state of the art. The proposed architecture operates at a
maximum operating frequency of 241.6 MHz and is able to process
1080p@60Hz with all possible variables block sizes specified in HEVC
standard as well as with motion vector search range of up to ±64 pixels.A codificação de vídeo tem sido usada em aplicações tais como, vídeovigilância,
vídeo-conferência, video streaming e armazenamento de vídeo.
Numa norma de codificação de vídeo, diversos algoritmos são combinados
para comprimir o vídeo. Contudo, um desses algoritmos, a estimação de
movimento é a tarefa mais complexa. Por isso, é necessário implementar esta
tarefa em tempo real usando arquiteturas de hardware apropriadas. Esta tese
propõe um algoritmo de estimação de movimento rápido bem como a sua
implementação em tempo real. Os resultados mostram que o algoritmo e a
arquitetura de hardware propostos têm melhor desempenho que os existentes.
A arquitetura proposta opera a uma frequência máxima de 241.6 MHz e é
capaz de processar imagens de resolução 1080p@60Hz, com todos os
tamanhos de blocos especificados na norma HEVC, bem como um domínio de
pesquisa de vetores de movimento até ±64 pixels
IMPLEMENTASI HEVC CODEC PADA PLATFORM BERBASIS FPGA
High Efficiency Video Coding (HEVC) telah di desain sebagai standar
baru untuk beberapa aplikasi video dan memiliki peningkatan performa dibanding
dengan standar sebelumnya. Meskipun HEVC mencapai efisiensi coding yang
tinggi, namun HEVC memiliki kekurangan pada beban pemrosesan tinggi dan
loading yang berat ketika melakukan proses encoding video. Untuk meningkatkan
performa encoder, kami bertujuan untuk mengimplementasikan HEVC codec
pada Zynq 7000 AP SoC.
Kami mencoba mengimplementasikan HEVC menggunakan tiga desain
sistem. Pertama, HEVC codec di implementasikan pada Zynq PS. Kedua, encoder
HEVC di implementasikan dengan hardware/software co-design. Ketiga,
mengimplementasikan sebagian dari encoder HEVC pada Zynq PL. Pada
implementasi kami menggunakan Xilinx Vivado HLS untuk mengembangkan
codec.
Hasil menunjukkan bahwa HEVC codec dapat di implementasikan pada
Zynq PS. Codec dapat mengurangi ukuran video dibanding ukuran asli video pada
format H.264. Kualitas video hampir sama dengan format H.264. Sayangnya,
kami tidak dapat menyelesaikan desain dengan hardware/software co-design
karena kompleksitas coding untuk validasi kode C pada Vivado HLS. Hasil lain,
sebagian dari encoder HEVC dapat di implementasikan pada Zynq PL, yaitu
HEVC 2D IDCT. Dari implementasi kami dapat mengoptimalkan fungsi loop
pada HEVC 2D dan 1D IDCT menggunakan pipelining. Perbandingan hasil
antara pipelining inner-loop dan outer-loop menunjukkan bahwa pipelining di
outer-loop dapat meningkatkan performa dilihat dari nilai latency
HIGH-THROUGHPUT AREA-EFFICIENT INTEGER TRANSFORMS FOR VIDEO CODING
Ph.DDOCTOR OF PHILOSOPH
Architectures for Adaptive Low-Power Embedded Multimedia Systems
This Ph.D. thesis describes novel hardware/software architectures for adaptive low-power embedded multimedia systems. Novel techniques for run-time adaptive energy management are proposed, such that both HW & SW adapt together to react to the unpredictable scenarios. A complete power-aware H.264 video encoder was developed. Comparison with state-of-the-art demonstrates significant energy savings while meeting the performance constraint and keeping the video quality degradation unnoticeable