Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-diffusion with nonequilibrium Green functions simulations, we show that quantum effects in the charge distribution and transport can reduce or amplify the impact of discrete traps in simulation of reliability resilience of scaled FinFETs

On Small Satellites for Oceanography: A Survey

The recent explosive growth of small satellite operations driven primarily from an academic or pedagogical need, has demonstrated the viability of commercial-off-the-shelf technologies in space. They have also leveraged and shown the need for development of compatible sensors primarily aimed for Earth observation tasks including monitoring terrestrial domains, communications and engineering tests. However, one domain that these platforms have not yet made substantial inroads into, is in the ocean sciences. Remote sensing has long been within the repertoire of tools for oceanographers to study dynamic large scale physical phenomena, such as gyres and fronts, bio-geochemical process transport, primary productivity and process studies in the coastal ocean. We argue that the time has come for micro and nano satellites (with mass smaller than 100 kg and 2 to 3 year development times) designed, built, tested and flown by academic departments, for coordinated observations with robotic assets in situ. We do so primarily by surveying SmallSat missions oriented towards ocean observations in the recent past, and in doing so, we update the current knowledge about what is feasible in the rapidly evolving field of platforms and sensors for this domain. We conclude by proposing a set of candidate ocean observing missions with an emphasis on radar-based observations, with a focus on Synthetic Aperture Radar.Comment: 63 pages, 4 figures, 8 table

Micro-manufacturing : research, technology outcomes and development issues

Besides continuing effort in developing MEMS-based manufacturing techniques, latest effort in Micro-manufacturing is also in Non-MEMS-based manufacturing. Research and technological development (RTD) in this field is encouraged by the increased demand on micro-components as well as promised development in the scaling down of the traditional macro-manufacturing processes for micro-length-scale manufacturing. This paper highlights some EU funded research activities in micro/nano-manufacturing, and gives examples of the latest development in micro-manufacturing methods/techniques, process chains, hybrid-processes, manufacturing equipment and supporting technologies/device, etc., which is followed by a summary of the achievements of the EU MASMICRO project. Finally, concluding remarks are given, which raise several issues concerning further development in micro-manufacturing

3D drift diffusion and 3D Monte Carlo simulation of on-current variability due to random dopants

In this work Random Discrete Dopant induced on-current variations have been studied using the Glasgow 3D atomistic drift/diffusion simulator and Monte Carlo simulations. A methodology for incorporating quantum corrections into self-consistent atomistic Monte Carlo simulations via the density gradient effective potential is presented. Quantum corrections based on the density gradient formalism are used to simultaneously capture quantum confinement effects. The quantum corrections not only capture charge confinement effects, but accurately represent the electron impurity interaction used in previous \textit{ab initio} atomistic MC simulations, showing agreement with bulk mobility simulation. The effect of quantum corrected transport variation in statistical atomistic MC simulation is then investigated using a series of realistic scaled devices nMOSFETs transistors with channel lengths 35 nm, 25 nm, 18nm, 13 nm and 9 nm. Such simulations result in an increased drain current variability when compared with drift diffusion simulation. The comprehensive statistical analysis of drain current variations is presented separately for each scaled transistor. The investigation has shown increased current variation compared with quantum corrected drift diffusion simulation and with previous classical MC results. Furthermore, it has been studied consistently the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano CMOS transistors. For the first time, a hierarchic simulation strategy to accurately transfer the increased on-current variability obtained from the ‘ab initio’ MC simulations to DD simulations is subsequently presented. The MC corrected DD simulations are used to produce target $I_D-V_G$ characteristics from which statistical compact models are extracted for use in preliminary design kits at the early stage of new technology development. The impact of transport variability on the accuracy of delay simulation are investigated in detail. Accurate compact models extraction methodology transferring results from accurate physical variability simulation into statistical compact models suitable for statistical circuit simulation is presented. In order to examine te size of this effect on circuits Monte Carlo SPICE simulations of inverter were carried out for 100 samples

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Simulation of charge-trapping in nano-scale MOSFETs in the presence of random-dopants-induced variability

The growing variability of electrical characteristics is a major issue associated with continuous downscaling of contemporary bulk MOSFETs. In addition, the operating conditions brought about by these same scaling trends have pushed MOSFET degradation mechanisms such as Bias Temperature Instability (BTI) to the forefront as a critical reliability threat. This thesis investigates the impact of this ageing phenomena, in conjunction with device variability, on key MOSFET electrical parameters. A three-dimensional drift-diffusion approximation is adopted as the simulation approach in this work, with random dopant fluctuations—the dominant source of statistical variability—included in the simulations. The testbed device is a realistic 35 nm physical gate length n-channel conventional bulk MOSFET. 1000 microscopically different implementations of the transistor are simulated and subjected to charge-trapping at the oxide interface. The statistical simulations reveal relatively rare but very large threshold voltage shifts, with magnitudes over 3 times than that predicted by the conventional theoretical approach. The physical origin of this effect is investigated in terms of the electrostatic influences of the random dopants and trapped charges on the channel electron concentration. Simulations with progressively increased trapped charge densities—emulating the characteristic condition of BTI degradation—result in further variability of the threshold voltage distribution. Weak correlations of the order of 10-2 are found between the pre-degradation threshold voltage and post-degradation threshold voltage shift distributions. The importance of accounting for random dopant fluctuations in the simulations is emphasised in order to obtain qualitative agreement between simulation results and published experimental measurements. Finally, the information gained from these device-level physical simulations is integrated into statistical compact models, making the information available to circuit designers

Nanowires: A route to efficient thermoelectric devices

Miniaturization of electronic devices aims at manufacturing ever smaller products, from mesoscopic to nanoscopic sizes. This trend is challenging because the increased levels of dissipated power demands a better understanding of heat transport in small volumes. A significant amount of the consumed energy is transformed into heat and dissipated to the environment. Thermoelectric materials offer the possibility to harness dissipated energy and make devices less energy-demanding. Heat-to-electricity conversion requires materials with a strongly suppressed thermal conductivity but still high electronic conduction. Nanowires can meet nicely these two requirements because enhanced phonon scattering at the surface and defects reduces the lattice thermal conductivity while electric conductivity is not deteriorated, leading to an overall remarkable thermoelectric efficiency. Therefore, nanowires are regarded as a promising route to achieving valuable thermoelectric materials at the nanoscale. In this paper, we present an overview of key experimental and theoretical results concerning the thermoelectric properties of nanowires. The focus of this review is put on the physical mechanisms by which the efficiency of nanowires can be improved. Phonon scattering at surfaces and interfaces, enhancement of the power factor by quantum effects and topological protection of electron states to prevent the degradation of electrical conductivity in nanowires are thoroughly discussed