Dielectric breakdown I: A review of oxide breakdown

This paper gives an overview of the dielectric breakdown in thin oxide layers on silicon. First test methods are discussed, followed by their application to the estimation of the oxide lifetime. The main part of the paper is devoted to the physical background of the intrinsic breakdown. Finally, defect-related or extrinsic breakdown is discussed

Influence of the spatial distribution of border traps in the capacitance frequency dispersion of Al2O3/InGaAs

In this paper, the capacitance frequency dispersion in strong accumulation of capacitance voltage curves has been studied for different high-k dielectric layers in MOS stacks. By studying experimental data at low (77 K) and room temperature (300 K), in oxides with different density of defects, it was possible reflect the spatial distribution of the defects in the capacitance frequency dispersion. The experimental data show that while at room temperature, the capacitance dispersion is dominated by the exchange of carriers from the semiconductor into oxide traps far away from the interface, at low temperature the oxide traps near the Al2O3/InGaAs interface are responsible for the frequency dispersion. The results indicate that the capacitance dispersion in strong accumulation reflect the spatial distribution of traps within the oxide, and that dielectric/semiconductor conduction band offset is a critical parameter for determining the capacitance dispersion for Al2O3/InGaAs based gate stacks.Fil: Palumbo, Félix Roberto Mario. Comisión Nacional de Energía Atómica; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Universidad Tecnológica Nacional; ArgentinaFil: Aguirre, Fernando Leonel. Universidad Tecnológica Nacional; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Comisión Nacional de Energía Atómica; ArgentinaFil: Pazos, Sebastián Matías. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Universidad Tecnológica Nacional; Argentina. Comisión Nacional de Energía Atómica; ArgentinaFil: Krylov, Igor. Technion - Israel Institute of Technology; IsraelFil: Winter, Roy. Technion - Israel Institute of Technology; IsraelFil: Eizenberg, Moshe. Technion - Israel Institute of Technology; Israe

Dielectric relaxation and Charge trapping characteristics study in Germanium based MOS devices with HfO2 /Dy2O3 gate stacks

In the present work we investigate the dielectric relaxation effects and charge trapping characteristics of HfO2 /Dy2O3 gate stacks grown on Ge substrates. The MOS devices have been subjected to constant voltage stress (CVS) conditions at accumulation and show relaxation effects in the whole range of applied stress voltages. Applied voltage polarities as well as thickness dependence of the relaxation effects have been investigated. Charge trapping is negligible at low stress fields while at higher fields (>4MV/cm) it becomes significant. In addition, we give experimental evidence that in tandem with the dielectric relaxation effect another mechanism- the so-called Maxwell-Wagner instability- is present and affects the transient current during the application of a CVS pulse. This instability is also found to be field dependent thus resulting in a trapped charge which is negative at low stress fields but changes to positive at higher fields.Comment: 27pages, 10 figures, 3 tables, regular journal contribution (accepted in IEEE TED, Vol.50, issue 10

Electrical characterization of the soft breakdown failure mode in MgO layers

The soft breakdown (SBD) failure mode in 20 nm thick MgO dielectric layers grown on Si substrates was investigated. We show that during a constant voltage stress, charge trapping and progressive breakdown coexist, and that the degradation dynamics is captured by a power-law time dependence. We also show that the SBD current-voltage (I-V) characteristics follow the power-law model I = aVb typical of this conduction mechanism but in a wider voltage window than the one reported in the past for SiO2. The relationship between the magnitude of the current and the normalized differential conductance was analyzed

Stress-Induced Leakage Current in p+ Poly MOS Capacitors with Poly-Si and Poly-Si0.7Ge0.3 Gate Material

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p+ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si0.7 Ge0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory device

Effects of sputtering and annealing temperatures on MOS capacitor with HfTiON gate dielectric

In this work, Al/HfTiON/n-Si capacitors with different sputtering and annealing temperatures are studied. Larger accumulation capacitance and flat-band voltage are observed for samples with higher sputtering or post-deposition annealing temperature. Gate conduction mechanisms are only affected by sputtering temperature slightly. The flat-band voltage shift and interface-state density at midgap under high-field gate injection and substrate injection are investigated, and the results imply electron detrapping in the gate dielectric. ©2009 IEEE.published_or_final_versionThe IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009), Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 209-21

Dielectric Breakdown in Chemical Vapor Deposited Hexagonal Boron Nitride

Insulating films are essential in multiple electronic devices because they can provide essential functionalities, such as capacitance effects and electrical fields. Two-dimensional (2D) layered materials have superb electronic, physical, chemical, thermal, and optical properties, and they can be effectively used to provide additional performances, such as flexibility and transparency. 2D layered insulators are called to be essential in future electronic devices, but their reliability, degradation kinetics, and dielectric breakdown (BD) process are still not understood. In this work, the dielectric breakdown process of multilayer hexagonal boron nitride (h-BN) is analyzed on the nanoscale and on the device level, and the experimental results are studied via theoretical models. It is found that under electrical stress, local charge accumulation and charge trapping/detrapping are the onset mechanisms for dielectric BD formation. By means of conductive atomic force microscopy, the BD event was triggered at several locations on the surface of different dielectrics (SiO2, HfO2, Al2O3, multilayer h-BN, and monolayer h-BN); BD-induced hillocks rapidly appeared on the surface of all of them when the BD was reached, except in monolayer h-BN. The high thermal conductivity of h-BN combined with the one-atom-thick nature are genuine factors contributing to heat dissipation at the BD spot, which avoids self-accelerated and thermally driven catastrophic BD. These results point to monolayer h-BN as a sublime dielectric in terms of reliability, which may have important implications in future digital electronic devices.Fil: Jiang, Lanlan. Soochow University; ChinaFil: Shi, Yuanyuan. Soochow University; China. University of Stanford; Estados UnidosFil: Hui, Fei. Soochow University; China. Massachusetts Institute of Technology; Estados UnidosFil: Tang, Kechao. University of Stanford; Estados UnidosFil: Wu, Qian. Soochow University; ChinaFil: Pan, Chengbin. Soochow University; ChinaFil: Jing, Xu. Soochow University; China. University of Texas at Austin; Estados UnidosFil: Uppal, Hasan. University of Manchester; Reino UnidoFil: Palumbo, Félix Roberto Mario. Comisión Nacional de Energía Atómica; Argentina. Universidad Tecnológica Nacional; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Lu, Guangyuan. Chinese Academy of Sciences; República de ChinaFil: Wu, Tianru. Chinese Academy of Sciences; República de ChinaFil: Wang, Haomin. Chinese Academy of Sciences; República de ChinaFil: Villena, Marco A.. Soochow University; ChinaFil: Xie, Xiaoming. Chinese Academy of Sciences; República de China. ShanghaiTech University; ChinaFil: McIntyre, Paul C.. University of Stanford; Estados UnidosFil: Lanza, Mario. Soochow University; Chin