Testability Analysis of Synchronous Sequential Circuits Based On Structural Data

Bounds on test sequence length can be used as a testability measure. We give a procedure to compute the upper bound on test sequence length for an arbitrary sequential circuit. We prove that the bound is exact for a certain class of circuits. Three design rules are specified to yield circuits with lower test sequence bounds

Mathematics in Software Reliability and Quality Assurance

This monograph concerns the mathematical aspects of software reliability and quality assurance and consists of 11 technical papers in this emerging area. Included are the latest research results related to formal methods and design, automatic software testing, software verification and validation, coalgebra theory, automata theory, hybrid system and software reliability modeling and assessment

Software test and evaluation study phase I and II : survey and analysis

Issued as Final report, Project no. G-36-661 (continues G-36-636; includes A-2568

Detection of hard faults in combinational logic circuits

ABSTRACT: Previous Work in identifying hard to test faults (HFs) -- The effect of reconvergent fanout and redundancy -- Testability measures (TMs)Using of ATPGs to detect HFs -- Previous use of cost in Testability analysis -- Review of automatic test pattern generation (ATPG) -- Fault modelling -- Single versus multiple path sensitization -- The four ATPG phases of deterministic gate level test generation -- Random test pattern generation and hybrid methods -- Review of the fan algorithm -- Backtrack reduction methods and the importance of heuristics -- Mixed graph -- binary decision diagram (GBDD) circuit model -- A review of graph techniques -- A review of binary decisions diagrams (BDDs) techniques -- gBDD -- graph binary decision diagrams -- Detection of hard faults using HUB -- Introduction to budgetary constraints -- The HUB algorithm -- Important HUB attributes -- Circuits characteristics of used for results -- Comparison of gBDD -- ATPG related results -- Fault simulation related results -- Hard fault detection

Test set generation and optimisation using evolutionary algorithms and cubical calculus.

As the complexity of modern day integrated circuits rises, many of the challenges associated with digital testing rise exponentially. VLSI technology continues to advance at a rapid pace, in accordance with Moore's Law, posing evermore complex, NP-complete problems for the test community. The testing of ICs currently accounts for approximately a third of the overall design costs and according to the Semiconductor Industry Association, the per-transistor test cost will soon exceed the per-transistor production cost. Given the need to test ICs of ever-increasing complexity and to contain the cost of test, the problems of test pattern generation, testability analysis and test set minimisation continue to provide formidable challenges for the research community. This thesis presents original work in these three areas. Firstly, a new method is presented for generating test patterns for multiple output combinational circuits based on the Boolean difference method and cubical calculus. The Boolean difference method has been largely overlooked in automatic test pattern generation algorithms due to its cumbersome, algebraic nature. It is shown that cubical calculus provides an elegant and economical technique for solving Boolean difference equations. Formal mathematical techniques are presented involving the Boolean difference and cubical calculus providing, a test pattern generation method that dispenses with the need for costly circuit simulations. The methods provide the basis for test generation algorithms which are suitable for computer implementation. Secondly, some of the core test pattern generation computations outlined above also provide the basis of a new method for computing testability measures such as controllability and observability. This method is effectively a very economical spin-off of the test pattern generation process using Boolean differences and cubical calculus.The third and largest part of this thesis introduces a new test set minimization algorithm, GA-MITS, based on an evolutionary optimization algorithm. This novel approach applies a genetic algorithm to find minimal or near minimal test sets while maintaining a given fault coverage. The algorithm is designed as a postprocessor to minimise test sets that have been previously generated by an ATPG system and is thus considered a static approach to the test set minimisation problem. It is shown empirically that GA-MITS is remarkably successful in minimizing test sets generated for the ISCAS-85 benchmark circuits and hence potentially capable of reducing the production costs of realistic digital circuits

Automatic Test Pattern Generation

The complexity of VLSI devices increases rapidly as technology increases, resulting in an increase in the difficulty of test generation. Traditional test generation algorithms target one fault of a fault set at a time to generate a test. This paper presents a brief overview of a few different approaches to concurrent test generation. Concurrent test generation is the process of generating tests by “concurrently” targeting multiple faults

Security and privacy in communication networks : Revised selected papers

Machine generated contents note: Session I Invited Talk -- Planet Dynamic or: How I Learned to Stop Worrying and Love Reflection / Jan Vitek -- Session II Concurrency -- JATO: Native Code Atomicity for Java / Gang Tan -- Ownership Types for Object Synchronisation / Jingling Xue -- Session III Security -- A Functional View of Imperative Information Flow / Martin Abadi -- End-to-end Multilevel Hybrid Information Flow Control / Lennart Beringer -- Succour to the Confused Deputy: Types for Capabilities / James Riely -- Types and Access Controls for Cross-Domain Security in Flash / Rob Johnson -- Session IV Static Analysis I -- Linear Approximation of Continuous Systems with Trapezoid Step Functions / Agostino Cortesi -- Signedness-Agnostic Program Analysis: Precise Integer Bounds for Low-Level Code / Peter J. Stuckey -- Hierarchical Shape Abstraction of Dynamic Structures in Static Blocks / Xavier Rival -- Contents note continued: Vinter: A Vampire-Based Tool for Interpolation (Tool Paper) / Andrei Voronkov -- Session V Static Analysis II -- Side-Effecting Constraint Systems: A Swiss Army Knife for Program Analysis / Vesal Vojdani -- Inference of Necessary Field Conditions with Abstract Interpretation / Manuel Fahndrich -- Session VI Language Design -- Lazy v. Yield: Incremental, Linear Pretty-Printing / Amr Sabry -- Dynamic Software Update for Message Passing Programs / Julian Rathke -- A Synchronous Language with Partial Delay Specification for Real-Time Systems Programming / Claire Pagetti -- Session VII Dynamic Analysis -- Concurrent Test Generation Using Concolic Multi-trace Analysis / Aarti Gupta -- Java Bytecode Instrumentation Made Easy: The DiSL Framework for Dynamic Program Analysis / Zhengwei Qi -- Session VIII Complexity and Semantics -- Indexed Realizability for Bounded-Time Programming with References and Type Fixpoints / Antoine Madet -- Contents note continued: A New Order-Theoretic Characterisation of the Polytime Computable Functions / Georg Moser -- A Dynamic Interpretation of the CPS Hierarchy / Dariusz Biernacki -- Session IX Invited Talk -- Scalable Formal Machine Models / Greg Morrisett -- Session X Program Logics and Verification -- Modular Verification of Concurrent Thread Management / Peizhi Shi -- A Case for Behavior-Preserving Actions in Separation Logic / Zhong Shao -- A Generic Cyclic Theorem Prover / Rasmus L. Petersen -- Decision Procedures over Sophisticated Fractional Permissions / Aquinas Hobor -- Session XI Invited Talk -- Mechanized Semantics for Compiler Verification / Xavier Leroy.419 page(s