RICIS Symposium 1992: Mission and Safety Critical Systems Research and Applications

This conference deals with computer systems which control systems whose failure to operate correctly could produce the loss of life and or property, mission and safety critical systems. Topics covered are: the work of standards groups, computer systems design and architecture, software reliability, process control systems, knowledge based expert systems, and computer and telecommunication protocols

A Simple Project Paradigm for Teaching Computer Architecture

This paper presents a teaching method for a possible computer architect by using a simple DCT project for an undergraduate-level computer architecture course. The goal of the project is to let students (two or three students per team) understand the concept of computer hardware and how to design a simple RISC-type 32-bit Instruction Set Architecture (ISA). The project consists of three different tasks: 1) D (Design) - Designing a processor at the abstract level; 2) C (Code) - Writing a simulation program for the ISA; and 3) T (Test) - Running a test program to verify each function of computer hardware. For the first task, students are required to design their own instruction sets, datapath, and control unit. For the second task, they write a simulation program by using a high-level language such as C/C++ or VHDL/Verilog based on the directions provided, and then they run a test program with the simulator to produce the results. The project has worked well for students since they responded favorably to the project and indicated that they learned the concepts of computer hardware and how to design computer architecture as a professional engineer

A coherent sequence of computer architecture laboratory assignments

The Computer Architecture course at the Rochester Institute of Technology (RIT) is taken by undergraduate students in their fourth year of study, after they have had an Introduction to Digital Systems, to Programming in C, and to Microprocessor Programming. The course gives students the computer hardware designer’s perspective, with an emphasis on complete logic design. The objective of the laboratory is the design, simulation and implementation of a processor in a reconfigurable hardware device. Each weekly laboratory assignment builds upon the previous one. The bottom-top design process starts with the design of a combinational logic Arithmetic and Logic Unit, of a Register File and Memory Blocks. The design of the Central Processing Unit is divided into the design of the Data Path and Control Unit. The Instruction Set Architecture is enforced, i.e. the students do not have to come up with their own instruction set. All students must follow general and individual design specifications. The latter are selected using a binary code assigned to each student. The value of each bit chooses between design alternatives such as: Von-Neumann versus Harvard, I/O Mapped versus Memory Mapped Peripherals, 3-bus versus 2-bus architecture, tri-state versus multiplexer data transfer, hardwired versus microprogrammed control unit etc. Each final processor implementation is different from any other, but can run the same machine code. The paper presents the organization of the laboratory sequence, describes each weekly assignment and the lesson

Division and conquer

Integer division is an important arithmetic operation on microprocessors. To derive integer division algorithms we present an unconvential approach: a derivation technique in a calculational style, that guarantees that the derived algorithms are correct. Four different algorithms are derived using this method: restoring division, non-restoring divsion, radix-4 division and division by multiplication. We translate these to descriptions into combinatorial circuits, expressed in Verilog code. Then the circuits are compiled on a Spartan-3 Generation FPGA. At the end, we compare the propagation delays and area requirements for these circuits. We show that the division by multiplication is much faster than the other methods, however it only works for 18 bit integers. Integer division is an important arithmetic operation on microprocessors. To derive integer division algorithms we present an unconvential approach: a derivation technique in a calculational style, that guarantees that the derived algorithms are correct. Four different algorithms are derived using this method: restoring division, non-restoring divsion, radix-4 division and division by multiplication. We translate these to descriptions into combinatorial circuits, expressed in Verilog code. Then the circuits are compiled on a Spartan-3 Generation FPGA. At the end, we compare the propagation delays and area requirements for these circuits. We show that the division by multiplication is much faster than the other methods, however it only works for 18 bit integers

IMPLEMENTATION OF SIMPLESCALAR PORTABLE INSTRUCTION SET ARCHITECTURE (PISA) ON FPGA

This report describes the current progress of final year project entitled Implementation of SimpleScalar Portable Instruction Set Architecture (PISA) on FPGA. The objectives of this study are to learn computer system architecture, to sharpen skill in programming and debugging a program and to complete study in Universiti Teknologi PETRONAS. Problem statements will explain the reasons behind of this study was conducted. Firstly, there are few microprocessors in the market currently can be reconfigurable. Secondly, there is a need to design a microprocessor which can be used freely for academic purposes. Thus, in this study, we will focus on the designing of a microprocessor that is reconfigurable, easily understood and freely available for academicals purposes. Methodology will describe way on how this project will be carried out. There are three main steps to be taken which are: 1) Studying the SimpleScalar instruction set architecture; 2) Programming and simulating by using VHDL programming language 3) Implementing the SimpleScalar architecture in VHDL and FPGA. In the Discussion, a detail contents regarding the project will be explained. Contents included are SimpleScalar's instruction format, register and operation cycle, software and hardware used in the project, the SimpleScalar implementation in VHDL and VHDL simulation. The further details will be discussed later. Finally, this report is concluded in the Conclusion. Recommendations describe the suggestions that can be done to the current project to improve them in the future

Sequential decomposition of operations and compilers optimization

Code optimization is an important area of research that has remarkable contributions in addressing the challenges of information technology. It has introduced a new trend in hardware as well as in software. Efforts that have been made in this context led to introduce a new foundation, both for compilers and processors. In this report we study different techniques used for sequential decomposition of mappings without using extra variables. We focus on finding and improving these techniques of computations. Especially, we are interested in developing methods and efficient heuristic algorithms to find the decompositions and implementing these methods in particular cases. We want to implement these methods in a compiler with an aim of optimizing code in machine language. It is always possible to calculate an operation related to K registers by a sequence of assignments using only these K registers. We verified the results and introduced new methods. We described In Situ computation of linear mapping by a sequence of linear assignments over the set of integers and investigated bound for the algorithm. We introduced a method for the case of boolean bijective mappings via algebraic operations over polynomials in GF(2). We implemented these methods using Mapl

Inclusive interaction design: bridging the gap between information visualization perception and color vision deficiency users

It’s becoming increasingly important to design for Inclusivity, meaning building products that are accessible to all type of users, namely color vision deficiency (CVD) deuteranope users. Along with that, we can say that Information Visualization plays a big role in the understanding of how ou world functions, since the amount of produced data (2.5 exabytes) is increasing every day. In this way, this project aims to bridge the gap between Information Visualization perception and color vision deficiency users, by exploring the effects that saturation as a variable, applied through an interaction design methodology approach, has on human visual perception. An interactive system was designe in order to explore the effects saturation had in both user’s perception. To perform the experiment, 12 trichromatic male participants were recruited and the selected graph’s colours were simulated into colours a CVD user would normally perceive. This experiment enabled to reach a range in which both trichromatic and CVD users perceive the information of a specific graph in an optimal way. Serving as a first assessment in potentially reaching a range that ensures the optimal visual perception of all types of Information Visualizations for both CVD an trichromatic users, this project intends to be used as a reference in future investigations, in order to improve the quality of life of users affected by this visual constraint

The Design of a Custom 32-Bit RISC CPU and Port to GCC Compiler Backend

This paper presents the design of a 32-bit RISC processor, which is then mapped to the backend of GCC so basic C code can be compiled successfully to the processor. There are many design decisions that go into the construction of a processor. The instruction set architecture gives away a lot of information regarding the individual instructions that the processor will have, the memory architecture, as well as how I/O peripherals will be handled. Additionally, the hardware implementation of the processor needs to be kept in mind when crating the design. Pipelining can often help with processor speed, while cache implementation can assist in memory speed. After designing the processor, GCC’s backend needs to be analyzed to port it to function with the processors individual opcodes. Once GCC can compile its C code to an assembly language which is able to assemble into machine code that matches up with the opcodes the processor was created for, the machine code can be written into the processor’s program memory and executed successfully. This paper also talks about different design decisions that are made during the process of creating a processor, as well as the general makeup of the GCC compilation process

ON THE FOUNDATIONS OF COMPUTABILITY THEORY

The principal motivation for this work is the observation that there are significant deficiencies in the foundations of conventional computability theory. This thesis examines the problems with conventional computability theory, including its failure to address discrepancies between theory and practice in computer science, semantic confusion in terminology, and limitations in the scope of conventional computing models. In light of these difficulties, fundamental notions are re-examined and revised definitions of key concepts such as “computer,” “computable,” and “computing power” are provided. A detailed analysis is conducted to determine desirable semantics and scope of applicability of foundational notions. The credibility of the revised definitions is ascertained by demonstrating by their ability to address identified problems with conventional definitions. Their practical utility is established through application to examples. Other related issues, including hidden complexity in computations, subtleties related to encodings, and the cardinalities of sets involved in computing, are examined. A resource-based meta-model for characterizing computing model properties is introduced. The proposed definitions are presented as a starting point for an alternate foundation for computability theory. However, formulation of the particular concepts under discussion is not the sole purpose of the thesis. The underlying objective of this research is to open discourse on alternate foundations of computability theory and to inspire re-examination of fundamental notions