The PreAmplifier ShAper for the ALICE TPC-Detector

In this paper the PreAmplifier ShAper (PASA) for the Time Projection Chamber (TPC) of the ALICE experiment at LHC is presented. The ALICE TPC PASA is an ASIC that integrates 16 identical channels, each consisting of Charge Sensitive Amplifiers (CSA) followed by a Pole-Zero network, self-adaptive bias network, two second-order bridged-T filters, two non-inverting level shifters and a start-up circuit. The circuit is optimized for a detector capacitance of 18-25 pF. For an input capacitance of 25 pF, the PASA features a conversion gain of 12.74 mV/fC, a peaking time of 160 ns, a FWHM of 190 ns, a power consumption of 11.65 mW/ch and an equivalent noise charge of 244e + 17e/pF. The circuit recovers smoothly to the baseline in about 600 ns. An integral non-linearity of 0.19% with an output swing of about 2.1 V is also achieved. The total area of the chip is 18 mm$^2$ and is implemented in AMS's C35B3C1 0.35 micron CMOS technology. Detailed characterization test were performed on about 48000 PASA circuits before mounting them on the ALICE TPC front-end cards. After more than two years of operation of the ALICE TPC with p-p and Pb-Pb collisions, the PASA has demonstrated to fulfill all requirements

Characterization and Modeling of High Power Microwave Effects in CMOS Microelectronics

The intentional use of high power microwave (HPM) signals to disrupt microelectronic systems is a substantial threat to vital infrastructure. Conventional methods to assess HPM threats involve empirical testing of electronic equipment, which provides no insight into fundamental mechanisms of HPM induced upset. The work presented in this dissertation is part of a broad effort to develop more effective means for HPM threat assessment. Comprehensive experimental evaluation of CMOS digital electronics was performed to provide critical information of the elementary mechanisms that govern the dynamics of HPM effects. Results show that electrostatic discharge (ESD) protection devices play a significant role in the behavior of circuits irradiated by HPM pulses. The PN junctions of the ESD protection devices distort HPM waveforms producing DC voltages at the input of the core logic elements, which produces output bit errors and abnormal circuit power dissipation. The dynamic capacitance of these devices combines with linear parasitic elements to create resonant structures that produce nonlinear circuit dynamics such as spurious oscillations. The insight into the fundamental mechanisms this research has revealed will contribute substantially to the broader effort aimed at identifying and mitigating susceptibilities in critical systems. Also presented in this work is a modeling technique based on scalable analytical circuit models that accounts for the non-quasi-static behavior of the ESD protection PN junctions. The results of circuit simulations employing these device models are in excellent agreement with experimental measurements, and are capable of predicting the threshold of effect for HPM driven non-linear circuit dynamics. For the first time, a deterministic method of evaluating HPM effects based on physical, scalable device parameters has been demonstrated. The modeling presented in this dissertation can be easily integrated into design cycles and will greatly aid the development of electronic systems with improved HPM immunity

Wireless Neurosensor for Full-Spectrum Electrophysiology Recordings during Free Behavior

SummaryBrain recordings in large animal models and humans typically rely on a tethered connection, which has restricted the spectrum of accessible experimental and clinical applications. To overcome this limitation, we have engineered a compact, lightweight, high data rate wireless neurosensor capable of recording the full spectrum of electrophysiological signals from the cortex of mobile subjects. The wireless communication system exploits a spatially distributed network of synchronized receivers that is scalable to hundreds of channels and vast environments. To demonstrate the versatility of our wireless neurosensor, we monitored cortical neuron populations in freely behaving nonhuman primates during natural locomotion and sleep-wake transitions in ecologically equivalent settings. The interface is electrically safe and compatible with the majority of existing neural probes, which may support previously inaccessible experimental and clinical research

LC oscillator chirp generator for LADAR applications

The design, layout, simulation, and testing of a signal generator integrated circuit (IC) intended to create a frequency modulated chirp signal used in Laser Assisted Detection and Ranging (LADAR) systems are described. LADAR systems function by illuminating a target with a laser beam and measuring the properties of the reflected signal. Applications include range finding, collision avoidance, terrain mapping, and facial recognition. The development and improvement of LADAR IC design can lead to miniaturized LADAR-on-chip systems that could significantly improve the usability and applications of said systems. Two designs, a fixed frequency oscillator bank (FFOB) and a voltage controlled oscillator bank (VCOB), were investigated as signal generators for chirped LADAR systems. The FFOB was designed to operate at 16 discrete frequencies ranging from 600 MHz to 2.1 GHz. The VCOB design offers a continuously variable frequency output ranging from 1 GHz to 3 GHz and outputs 32 discrete frequencies ranging from 1.5 GHz to 3.05 GHz in the suggested configuration. The FFOB design consists of 16 individual oscillators that are each controlled by a logical input pin on the package. In contrast, the VCOB design consists of eight oscillators, each with a tunable frequency and are cycled automatically by an on-chip digital counter circuit. All designs were completed in the IBM CMRF7SF process. The FFOB IC design was manufactured and packaged by MOSIS, and testing of the FFOB chip was completed. The VCOB IC was was designed to improve the performance of the FFOB signal generator by lowering power consumption, reducing signal distortion, increasing the number of the steps in the chirped waveform, and increasing bandwidth

Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip

Design, Characterization and Analysis of Component Level Electrostatic Discharge (ESD) Protection Solutions

Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit\u27s operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology requires custom design of effective ESD protection solution. And usually the design window will shrinks due to the evolving of the technology becomes smaller and smaller. The ESD related failure is a major IC reliability concern and results in a loss of millions dollars each year in the semiconductor industry. To emulate the real word stress condition, several ESD stress models and test methods have been developed. The basic ESD models are Human Body model (HBM), Machine Mode (MM), and Charge Device Model (CDM). For the system-level ESD robustness, it is defined by different standards and specifications than component-level ESD requirements. International Electrotechnical Commission (IEC) 61000-4-2 has been used for the product and the Human Metal Model (HMM) has been used for the system at the wafer level. Increasingly stringent design specifications are forcing original equipment manufacturers (OEMs) to minimize the number of off-chip components. This is the case in emerging multifunction mobile, industrial, automotive and healthcare applications. It requires a high level of ESD robustness and the integrated circuit (IC) level, while finding ways to streamline the ESD characterization during early development cycle. To enable predicting the ESD performance of IC\u27s pins that are directly exposed to a system-level stress condition, a new the human metal model (HMM) test model has been introduced. In this work, a new testing methodology for product-level HMM characterization is introduced. This testing framework allows for consistently identifying ESD-induced failures in a product, substantially simplifying the testing process, and significantly reducing the product evaluation time during development cycle. It helps eliminates the potential inaccuracy provided by the conventional characterization methodology. For verification purposes, this method has been applied to detect the failures of two different products. Addition to the exploration of new characterization methodology that provides better accuracy, we also have looked into the protection devices itself. ICs for emerging high performance precision data acquisition and transceivers in industrial, automotive and wireless infrastructure applications require effective and ESD protection solutions. These circuits, with relatively high operating voltages at the Input/Output (I/O) pins, are increasingly being designed in low voltage Complementary Metal-Oxide-Semiconductor (CMOS) technologies to meet the requirements of low cost and large scale integration. A new dual-polarity SCR optimized for high bidirectional blocking voltages, high trigger current and low capacitance is realized in a sub 3-V, 180-nm CMOS process. This ESD device is designed for a specific application where the operating voltage at the I/O is larger than that of the core circuit. For instance, protecting high voltage swing I/Os in CMOS data acquisition system (DAS) applications. In this reference application, an array of thin film resistors voltage divider is directly connected to the interface pin, reducing the maximum voltage that is obtained at the core device input down to ± 1-5 V. Its ESD characteristics, including the trigger voltage and failure current, are compared against those of a typical CMOS-based SCR. Then, we have looked into the ESD protection designs into more advanced technology, the 28-nm CMOS. An ESD protection design builds on the multiple discharge-paths ESD cell concept and focuses the attention on the detailed design, optimization and realization of the in-situ ESD protection cell for IO pins with variable operation voltages. By introducing different device configurations fabricated in a 28-nm CMOS process, a greater flexibility in the design options and design trade-offs can be obtained in the proposed topology, thus achieving a higher integration and smaller cell size definition for multi-voltage compatibility interface ESD protection applications. This device is optimized for low capacitance and synthesized with the circuit IO components for in-situ ESD protection in communication interface applications developed in a 28-nm, high-k, and metal-gate CMOS technology. ESD devices have been used in different types of applications and also at different environment conditions, such as high temperature. At the last section of this research work, we have performed an investigation of several different ESD devices\u27 performance under various temperature conditions. And it has been shown that the variations of the device structure can results different ESD performance, and some devices can be used at the high temperature and some cannot. And this investigation also brings up a potential threat to the current ESD protection devices that they might be very vulnerable to the latch-up issue at the higher temperature range

An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis

Accepted versio

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields