UPPAAL in 1995

UPPAAL is a tool suite for automatic verification of safety andbounded liveness properties of real-time systems modeled as networks of timed automata[12, 9, 4], developed during the past two years. In this paper, we summarizethe main features of UPPAAL in particular its various extensions developed in 1995as well as applications to various case-studies, review and provide pointers to thetheoretical foundation

Compositional Safety Logics

In this paper we present a generalisation of a promising compositional model-checking technique introduced for finite-state systems by Andersen in [And95] and extended to networks of timedautomata by Larsen et al in [LPY95a, LL95, LPY95b, KLL+97a].In our generalized setting, programs are modelled as arbitrary(possibly infinite-state) transition systems and verified with respectto properties of a basic safety logic. As the fundamentalprerequisite of the compositional technique, it is shown how logicalproperties of a parallel program may be transformed intonecessary and sufficient properties of components of the program.Finally, a set of axiomatic laws are provided useful forsimplifying formulae and complete with respect to validity andunsatisfiability

Efficient Timed Reachability Analysis using Clock Difference Diagrams

One of the major problems in applying automatic verication tools to industrial-size systems is the excessive amount of memory required during the state-space exploration of amodel. In the setting of real-time, this problem of state-explosion requires extra attention as information must be kept not only on the discrete control structure but also on the values of continuous clock variables. In this paper, we present Clock Dierence Diagrams, CDD's, a BDD-like data-structure forrepresenting and eectively manipulating certain non-convex subsets of the Euclidean space, notably those encountered during verication of timed automata. A version of the real-time verication tool Uppaal using CDD's as a compact datastructurefor storing explored symbolic states has been implemented. Our experimental results demonstrate signicant space-savings: for 8 industrial examples, the savings are between 46%and 99% with moderate increase in runtime. We further report on how the symbolic state-space exploration itself may be carried out using CDD's

A comparative assessment of collaborative business process verification approaches.

Industry 4.0 is a key strategic trend of the economy. Virtual factories are key building blocks for Industry 4.0 where product design processes, manufacturing processes and general collaborative business processes across factories and enterprises are integrated. In the context of EU H2020 FIRST (vF Interoperation suppoRting buSiness innovaTion) project, end users of vFs are not experts in business process modelling to guarantee correct collaborative business processes for realizing execution. To enable automatic execution of business processes, verification is an important step at the business process design stage to avoid errors at runtime. Research in business process model verification has yielded a plethora of approaches in form of languages and tools that are based on Petri nets family and temporal logic. However, no report specifically targets and presents a comparative assessment of these approaches based on criteria as one we propose. In this paper we present an assessment of the most common verification approaches based on their expressibility, flexibility, suitability and complexity. We also look at how big data impacts the business process verification approach in a data-rich world

Action and predicate safety of hybrid processes

Abstract In this paper, we study two kinds of safety properties for hybrid processes, namely safety for actions and safety for predicates on model variables. We give an algebraic specification of these safety properties using the process algebra HyPA, and show how to reduce the question of safety of a linear process specification to the question of safety of its sub-processes. As an example, we study a variant of Fischer¿s protocol, in which there can be a relative error between the clocks that are used

Modelling of the real-time control system for a nuclear fusion experiment using Uppaal

Recent nuclear fusion experiments require a real-time control system to improve plasma confinement and suppress its magneto hydrodynamic (MHD) instabilities. Referring to the RFX experiment (Padua, Italy), we want to model its real-time control system with the tool Uppaal. The main objective of this thesis is to analyse how the system's behavior changes according to the different schedulers and their configurations. Two categories of scheduler for real-time threads are considered

Utilization of timed automata as a verification tool for real-time security protocols

Thesis (Master)--Izmir Institute of Technology, Computer Engineering, Izmir, 2010Includes bibliographical references (leaves: 85-92)Text in English; Abstract: Turkish and Englishxi, 92 leavesTimed Automata is an extension to the automata-theoretic approach to the modeling of real time systems that introduces time into the classical automata. Since it has been first proposed by Alur and Dill in the early nineties, it has become an important research area and been widely studied in both the context of formal languages and modeling and verification of real time systems. Timed automata use dense time modeling, allowing efficient model checking of time-sensitive systems whose correct functioning depend on the timing properties. One of these application areas is the verification of security protocols. This thesis aims to study the timed automata model and utilize it as a verification tool for security protocols. As a case study, the Neuman-Stubblebine Repeated Authentication Protocol is modeled and verified employing the time-sensitive properties in the model. The flaws of the protocol are analyzed and it is commented on the benefits and challenges of the model

Third Dutch model checking day, Eindhoven, November 7, 2001 : proceedings

This report contains the preliminary proceedings of the third Dutch Model Checking Day, held on 7th November 2001 at the Technische Universiteit Eindhoven. Model checking is an automatic technique for verifying hardware and software systems. The advance of the research in this area in the past few years has lead to a significant improvement of the model checking tools. Successful applications of model checking have been reported in the verification of a wide variety of systems, like complex sequential circuit designs and communication protocols. An important evidence of the great practical potential of model checking is the development of in-house model checking tools within the major companies from the information and telecommunication industry. The objective of the Model Checking Day was to bring together researchers and practitioners from academia and industry who are interested in model checking. The presentations featured both practical and theoretical advances in the area. This includes new techniques and methodologies, as well as experience with their application in various areas, such as embedded systems, communication protocols, hardware components, production processes, etc. Besides this, the Model Checking Day provided an opportunity to exchange experiences, and to have discussions about new ideas and the latest developments in the area. This proceedings contains contributions related to the presentations on this day, details are given in the table of contents. The Model Checking Day received generous support from the Formal Methods Group of the Technische Universiteit Eindhoven and the research school IPA (Institute for Programming research and Algorithmics). At this point I would like to thank the members of the program committee Dragan Bosnacki (TU/e Computer Science), Leszek Holenderski (Philips Research) and Jeroen Voeten (TU/e Electrical Engineering), and the secretary Elize Russell (TU/e Computer Science) for all their work