Millimeter-Wave Concurrent Dual-Band Sige Bicmos Rfic Phased-Array Transmitter and Components

A concurrent dual-band phased-array transmitter (TX) and its constituent components are studied in this dissertation. The TX and components are designed for the unlicensed bands, 22–29 and 57–64 GHz, using a 0.18-μm BiCMOS technology. Various studies have been done to design the components, which are suitable for the concurrent dual-band phased-array TX. The designed and developed components in this study are an attenuator, switch, phase shifter, power amplifier and power divider. Attenuators play a key role in tailoring main beam and side-lobe patterns in a phased-array TX. To perform the function in the concurrent dual-band phased-array TX, a 22–29 and 57–64 GHz concurrent dual-band attenuator with low phase variations is designed. Signal detection paths are employed at the output of the phased-array TX to monitor the phase and amplitude deviations/errors, which are larger in the high-frequency design. The detected information enables the TX to have an accurate beam tailoring and steering. A 10–67 GHz wide-band attenuator, covering the dual bands, is designed to manipulate the amplitude of the detected signal. New design techniques for an attenuator with a wide attenuation range and improved flatness are proposed. Also, a topology of dual-function circuit, attenuation and switching, is proposed. The switching turns on and off the detection path to minimize the leakages while the path is not used. Switches are used to minimize the number of components in the phased-array transceiver. With the switches, some of the bi-directional components in the transceiver such as an attenuator, phase shifter, filter, and antenna can be shared by the TX and receiver (RX) parts. In this dissertation, a high-isolation switch with a band-pass filtering response is proposed. The band-pass filtering response suppresses the undesired harmonics and intermodulation products of the TX. Phase shifters are used in phased-array TXs to steer the direction of the beam. A 24-GHz phase shifter with low insertion loss variation is designed using a transistor-body-floating technique for our phased-array TX. The low insertion loss variation minimizes the interference in the amplitude control operation (by attenuator or variable gain amplifier) in phased-array systems. BJTs in a BiCMOS process are characterized across dc to 67 GHz. A novel characterization technique, using on-wafer calibration and EM-based de-embedding both, is proposed and its accuracy at high frequencies is verified. The characterized BJT is used in designing the amplifiers in the phased-array TX. A concurrent dual-band power amplifier (PA) centered at 24 and 60 GHz is proposed and designed for the dual-band phased-array TX. Since the PA is operating in the dual frequency bands simultaneously, significant linearity issues occur. To resolve the problems, a study to find significant intermodulation (IM) products, which increase the third intermodulation (IM3) products most, has been done. Also, an advanced simulation and measurement methodology using three fundamental tones is proposed. An 8-way power divider with dual-band frequency response of 22–29 and 57–64 GHz is designed as a constituent component of the phased-array TX

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Design, Optimization and Fabrication of Amorphous Silicon Tunable RF MEMS Inductors and Transformers

High performance inductors are playing an increasing role in modern communication systems. Despite the superior performance offered by discrete components, parasitic capacitances from bond pads, board traces and packaging leads reduce the high frequency performance and contribute to the urgency of an integrated solution. Embedded inductors have the potential for significant increase in reliability and performance of the IC. Due to the driving force of CMOS integration and low costs of silicon-based IC fabrication, these inductors lie on a low resistivity silicon substrate, which is a major source of energy loss and limits the frequency response. Therefore, the quality factor of inductors fabricated on silicon continues to be low. The research presented in this thesis investigates amorphous Si and porous Si to improve the resistivity of Si substrates and explores amorphous Si as a structural material for low temperature MEMS fabrication. Planar inductors are built-on undoped amorphous Si in a novel application and a 56% increase in quality factor was measured. Planar inductors are also built-on a porous Si and amorphous Si bilayer and showed 47% improvement. Amorphous Si is also proposed as a low temperature alternative to polysilicon for MEMS devices. Tunable RF MEMS inductors and transformers are fabricated based on an amorphous Si and aluminum bimorph coil that is suspended and warps in a controllable manner. The 3-D displacement is accurately predicted by thermomechanical simulations. The tuning of the devices is achieved by applying a DC voltage and due to joule heating the air gap can be adjusted. A tunable inductor with a 32% tuning range from 5.6 to 8.2 nH and a peak Q of 15 was measured. A transformer with a suspended coil demonstrated a 24% tuning range of the mutual coupling between two stacked windings. The main limitation posed by post-CMOS integration is a strict thermal budget which cannot exceed a critical temperature where impurities can diffuse and materials properties can change. The research carried out in this work accommodates this temperature restriction by limiting the RF fabrication processes to 150°C to facilitate system integration on silicon

Compact modelling in RF CMOS technology

With the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years. Today, the standard CMOS technology has become a popular choice for realizing radio frequency (RF) applications. The focus of the thesis is on device compact modelling methodologies in RF CMOS. Compact models oriented to integrated circuit (ICs) computer automatic design (CAD) are the key component of a process design kit (PDK) and the bridge between design houses and foundries. In this work, a novel substrate model is proposed for accurately characterizing the behaviour of RF-MOSFETs with deep n-wells (DNW). A simple test structure is presented to directly access the substrate parasitics from two-port measurements in DNWs. The most important passive device in RFIC design in CMOS is the spiral inductor. A 1-pi model with a novel substrate network is proposed to characterize the broadband loss mechanisms of spiral inductors. Based on the proposed 1-pi model, a physics-originated fully-scalable 2-pi model and model parameter extraction methodology are also presented for spiral inductors in this work. To test and verify the developed active and passive device models and model parameter extraction methods, a series of RF-MOSFETs and planar on-chip spiral inductors with different geometries manufactured by employing standard RF CMOS processes were considered. Excellent agreement between the measured and the simulated results validate the compact models and modelling technologies developed in this work

Extension of 0.18µm standard CMOS technology operating range to the microwave and millimetre-wave regime

There is an increasing interest in building millimetre-wave circuits on standard digital complementary metal oxide semiconductor (CMOS) technology for applications such as wireless local area networks (WLAN), automotive radar and remote sensing. This stems from the existing low cost, well-developed, high yield infrastructure for mass production. The overall aim of this thesis is to extend the operating range of 0.18um standard logic CMOS technology to millimetre-wave regime. To this end, microwave and millimetre-wave design, optimisation and modelling methodologies for active and passive devices and low noise circuit implementation are described. As part of the evaluation, new systematic and modular ways of making high performance passive and active devices such as spiral inductors, slow-wave coplanar waveguide (CPW) transmission lines, comb capacitors and NMOS transistors are proposed, designed, simulated, fabricated, modelled and analysed. Small-signal and noise de-embedding techniques are developed and verified up to 110 GHz, providing an increased accuracy in the device model, leading to a robust design at millimetre-wave frequencies. Reduced substrate losses resulting in increased quality factor are presented for optimised spiral inductor designs, featuring patterned floating shield (PFS), enabling improved matching network and a reduced chip area. Based on the proposed shielded slow-wave CPW, both the line attenuation and structure length are decreased, resulting in a more compact and simplified circuit design. An optimised transistor design, aimed at reducing the layout parasitic effects, was realised. The optimisation led to a significant improvement in the gain and noise performance of the transistor, extending its operation beyond the cut-off frequency (ft). By combining all the optimised components, low noise amplifiers (LNAs) operating at 25 GHz and 40 GHz were implemented and compared. These LNAs demonstrate state-of-the-art performance, with the 40 GHz LNA exhibiting the highest gain and lowest noise performance of any LNA reported using 0.18um CMOS technology. On the other hand, the 25 GHz LNA showed a comparable performance to other reported results in literature using several topologies implemented in CMOS technology. These findings will provide a framework for expansion to smaller CMOS technology nodes with the view of extending to sub millimetre-wave frequencies

On-chip Spiral Inductor/transformer Design And Modeling For Rf Applications

Passive components are indispensable in the design and development of microchips for high-frequency applications. Inductors in particular are used frequently in radio frequency (RF) IC\u27s such as low-noise amplifiers and oscillators. High performance inductor has become one of the critical components for voltage controlled oscillator (VCO) design, for its quality factor (Q) value directly affects the VCO phase noise. The optimization of inductor layout can improve its performance, but the improvement is limited by selected technology. Inductor performance is bounded by the thin routing metal and small distance from lossy substrate. On the other hand, the in-accurate inductor modeling further limits the optimization process. The on-chip inductor has been an important research topic since it was first proposed in early 1990\u27s. Significant amount of study has been accomplished and reported in literature; whereas some methods have been used in industry, but not released to public. It is of no doubt that a comprehensive solution is not exist yet. A comprehensive study of previous will be first address. Later author will point out the in-adequacy of skin effect and proximity effect as cause of current crowding in the inductor metal. A model method embedded with new explanation of current crowding is proposed and its applicability in differential inductor and balun is validated. This study leads to a robust optimization routine to improve inductor performance without any addition technology cost and development

Miniaturization of on-chip passive electronic devices by silicon nitride self-rolled-up membrane microtube nanotechnology

Miniaturization of the commonly used on-chip lumped elements is highly desirable to enhance the density, performance and functionality of integrated circuits (ICs) working from DC to millimeter wave frequency band. Numerous improvement methods have been demonstrated but all fail to fundamentally solve the intrinsic drawbacks of currently used planar spiral platforms for passive lumped elements. A new design platform based on self-rolled-up membrane (S-RuM) nanotechnology that “processes like 2-D and functions like 3-D” is proposed for constructing on-chip three-dimensional (3-D) rolled-up microtube structures. By taking lumped inductors and transformers, this thesis demonstrates a global solution to obtain on-chip lumped elements with an extremely small on-chip footprint and almost complete immunity to substrate issues. The fabrication process of S-RuM lumped elements is designed to be CMOS compatible with a clear trend to achieving 100% fabrication yield. A quasi-dynamic finite element method (FEM) is established to precisely calculate the dimensions of rolled-up structures, which allows an accurate simulation of the electrical performance of S-RuM lumped passive devices by physical modeling. The design of the S-RuM inductor from FEM structural simulation to physical model electrical simulation is demonstrated, and its physical model is further integrated into the commercial Advanced Design System (ADS) software as a design kit for circuit-level simulation. Full wave FEM 3-D modeling of ICs including S-RuM inductors in the layouts is enabled by EMPro and ADS FEM co-simulation. A simple high pass filter is used as an example to show the S-RuM IC design process. A clear trend to save 38% ~ 50% chip size is also shown in active IC examples by replacing planar spiral inductors with S-RuM inductors. As a unit device, the S-RuM inductor can be used to build other passive elements like transformers. So, the S-RuM transformer is also investigated in this thesis. The thermal and mechanical reliability of the S-RuM platform are tested by using rapid thermal annealing (RTA) and nano-indention, which provide data for further packaging S-RuM lumped passive devices and applications in a power electronics. All samples are fabricated on a 1 to 10 cm p-type silicon substrate. Cu based S-RuM inductor samples show a 119 nH/mm2 inductance density, Q factor of 3 @ 8 GHz, a 0.3 nH to 2.4 nH inductance range, a self-resonant-frequency (SRF) of ~20 GHz, 250 C thermal stability, and 48.6 N/m stiffness. Au based S-RuM transformer samples shows a 1.52:1 turn ratio (n), 0.99 mutual magnetic coupling coefficient (km), and 0.392 maximum available gain at 8.6 GHz with a footprint (S) of only ~0.0085 mm2. The corresponding index of transformer performance ((n∙ km)/S ) is 177, which is ~2 than that of the best on-chip planar transformer reported so far with a similar turn ratio. The performance of the S-RuM transformers is stable at temperatures up to 250 ºC, and the hardness of the rolled-up structures is as high as 270.2 N/m

Physical Aspects of VLSI Design with a Focus on Three-Dimensional Integrated Circuit Applications

This work is on three-dimensional integration (3DI), and physical problems and aspects of VLSI design. Miniaturization and highly complex integrated systems in microelectronics have led to the 3DI development as a promising technological approach. 3DI offers numerous advantages: Size, power consumption, hybrid integration etc., with more thermal problems and physical complexity as trade-offs. We open this work by presenting the design and testing of an example 3DI system, to our knowledge the first self-powering system in a three-dimensional SOI technology. The system uses ambient optical energy harvested by a photodiode array and stored in an integrated capacitor. An on-chip metal interconnect network, beyond its designed role, behaves as a parasitic load vulnerable to electromagnetic coupling. We have developed a spatially-dependent, transient Green's Function based method of calculating the response of an interconnect network to noise. This efficient method can model network delays and noise sensitivity, which are involved problems in both planar and especially in 3DICs. Three-dimensional systems are more susceptible to thermal problems, which also affect VLSI with high power densities, of complex systems and under extreme temperatures. We analytically and experimentally investigate thermal effects in ICs. We study the effects of non-uniform, non-isotropic thermal conductivity of the typically complex IC material system, with a simulator we developed including this complexity. Through our simulations, verified by experiments, we propose a method of cooling or directionally heating IC regions. 3DICs are suited for developing wireless sensor networks, commonly referred to as ``smart dust.'' The ideal smart dust node includes RF communication circuits with on-chip passive components. We present an experimental study of on-chip inductors and transformers as integrated passives. We also demonstrate the performance improvement in 3DI with its lower capacitive loads. 3DI technology is just one example of the intense development in today's electronics, which maintains the need for educational methods to assist student recruitment into technology, to prepare students for a demanding technological landscape, and to raise societal awareness of technology. We conclude this work by presenting three electrical engineering curricula we designed and implemented, targeting these needs among others

Copper / low-k technological platform for the fabrication of high quality factor above-IC passive devices

Modern communication devices demand challenging specifications in terms of miniaturization, performance, power consumption and cost. Every new generation of radio frequency integrated circuits (RF-ICs) offer better functionality at reduced size, power consumption and cost per device and per integrated function. Passive devices (resistors, inductors, capacitors, antennas and transmission lines) represent an important part of the cost and size of RF circuits. These components have not evolved at the same level of the transistor devices, especially because their performance is strongly degenerated when they scale down in size. The low resistivity silicon used to build the transistors also imposes prohibitive levels of RF losses to these passive devices. Radio frequency microelectromechanical systems (RF MEMS) are enabling technologies capable to bring significant improvement in the electrical performances and expressive size and cost reduction of these functions, with unparallel introduction of new functionalities, unimaginable to attain when using bulky, externally connected discrete components. High quality factor (Q) inductors are amongst ones of the most needed components in RF circuits and at the same time ones that are most affected by thin metallization and substrate related losses, demanding considerable research effort. This thesis presents a contribution toward the development of thick metal fabrication technologies, covering also the design, modeling and characterization of high quality factor and high self-resonant frequency (SRF) RF MEMS passive devices, with a special emphasis on spiral inductors. A new approach using damascene-like interconnect fabrication steps associated to low κ dielectrics (polyimide), highly-conductive thick copper electroplating, chemical mechanical polishing (CMP) and tailored substrate properties delivered quality factors in excess of 40 and self resonant frequencies in excess of 10 GHz, performances in the current state-of-the-art for integrated spiral inductors built on top of silicon wafers. Furthermore, the developed process steps are compatible with back-end processing used to fabricate modern IC interconnects and have a low thermal budget (< 250 °C), what makes it a good choice to build above-IC passives without degenerating the performance of passivated RF-CMOS circuits. Deep reactive ion etching (DRIE) of quartz substrates was also studied for the fabrication of spiral inductors, offering excellent RF performances (Q exceeding 40 and SRF exceeding 7 GHz). A new doubly-functional quartz packaging concept for RF MEMS devices was developed. This technique process both sides of the packaging wafer: the top is used to embed high quality factor copper inductors while the bottom is thermo-mechanically bonded to another RF MEMS wafer, offering a semi-hermetic SU-8 epoxy-based seal. The bonding process was optimized for high yield, to be compatible with SF6-plasma-released MEMS and to present low level of RF losses. Band pass filters for the GSM (1.8 GHz) and WLAN (5.2 GHz) standards were fabricated and characterized by RF measurements and full wave electromagnetic simulations. Although further development is need in order to predict the frequency response accurately, insertion losses as low as 1.2 dB were demonstrated, levels that cannot be usually attained using on-chip passives. Systematic analysis, RF measurements, electromagnetic simulations and equivalent circuit extraction were used to model the behavior of the fabricated devices and establish a methodology to deliver optimum performances for a given technological profile and specified performance targets (quality factor, inductance and frequency bandwidth). A simple yet accurate physics-based analytical model for spiral inductors was developed and proved to be accurate in terms of loss estimation for thick metal layers. This model is capable to accurately describe the frequency-dependent behavior of the device below its first resonant frequency over a large device design space. The model was validated by both measurements and full wave electromagnetic simulations and is well suited to perform numeric optimization of designs. The proposed models were also systematized in a Matlab® toolbox