Complete Nanowire Crossbar Framework Optimized for the Multi-Spacer Patterning Technique

Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this paper, we propose for the first time the utilization of the multi-spacer patterning technique to fabricate nanowire crossbars with a high cross-point density up to 1010 cm−2. We propose a novel decoder fabrication method that can be included in a process dedicated to the multi-spacer patterning technique. We address the technology problems consisting in the variability and fabrication complexity at the design level by optimizing the encoding scheme. We show an overall reduction of the variability by 18% and a cancelation of the fabrication complexity overhead

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devices, whose practical realization has been demonstrated within a broad range of different technologies. For electron devices, the memristive functionality can be generally attributed to a material state modification, whose dynamics can be engineered to target a specific application. In this review paper, we show that trap charging dynamics can explain some of the memristive effects previously reported for Schottky-barrier field-effect Si nanowire transistors (SB SiNW FETs). Moreover, the SB SiNW FETs do show additional memristive functionality due to trap charging at the metal/ semiconductor surface. The combination of these two memristive effects into multiterminal metal–oxide–semiconductor field-effect transistor (MOSFET) devices gives rise to new opportunities for both memory and logic applications as well as new sensors based on the physical mechanism that originate memristance. In the special case of four-terminal memristive Si nanowire devices, which are presented for the first time in this paper, enhanced functionality is demonstrated. Finally, the multiterminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid complementary metal–oxide–semiconductor (CMOS) cofabrication with a CMOS-compatible process

Cutting Edge Nanotechnology

The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters

Hybrid photonic integrated circuits for neuromorphic computing [Invited]

The burgeoning of artificial intelligence has brought great convenience to people’s lives as large-scale computational models have emerged. Artificial intelligence-related applications, such as autonomous driving, medical diagnosis, and speech recognition, have experienced remarkable progress in recent years; however, such systems require vast amounts of data for accurate inference and reliable performance, presenting challenges in both speed and power consumption. Neuromorphic computing based on photonic integrated circuits (PICs) is currently a subject of interest to achieve high-speed, energy-efficient, and low-latency data processing to alleviate some of these challenges. Herein, we present an overview of the current photonic platforms available, the materials which have the potential to be integrated with PICs to achieve further performance, and recent progress in hybrid devices for neuromorphic computing

Nanoscale Memristive Devices for Memory and Logic Applications.

As the building block of semiconductor electronics, field effect transistor (FET), approaches the sub 100 nm regime, a number of fundamental and practical issues start to emerge such as short channel effects that prevent the FET from operating properly and sub-threshold slope non-scaling that leads to increased power dissipation. In terms of nonvolatile memory, it is generally believed that transistor based Flash memory will approach the end of scaling within about a decade. As a result, novel, non-FET based devices and architectures will likely be needed to satisfy the growing demands for high performance memory and logic electronics applications. In this thesis, we present studies on nanoscale resistance switching devices (memristive devices). The device shows excellent resistance switching properties such as fast switching time ( 10^6), good data retention (> 6 years) and programming endurance (> 10^5). The studies suggest that the nonvolatile resistance switching in a nanoscale a-Si resistive switch is caused by the formation of a single conductive filament within 10 nm range near the bottom electrode. New functionalities, such as multi-bit switching with partially formed filaments, can be obtained by controlling the resistance switching process through current programming. As digital memory devices, the devices are ideally suited in the crossbar architecture which offers ultra-high density and intrinsic defect tolerance capability. As an example, a high-density (2 Gbits/cm^2) 1kb crossbar memory was demonstrated with excellent uniformity, high yield (> 92%) and ON/OFF ratio (> 10^3), proving its promising aspects for memory and reconfigurable logic applications. Furthermore, we demonstrated that properly designed devices can exhibit controlled analog switching behavior and function as flux controlled memristor devices. The analog memristors can be used in biology-inspired neuromorphic circuits in which signal processing efficiency orders of magnitude higher than conventional digital computer systems can be reached. As a prototype illustration, we showed Spike Timing Dependent Plasticity (STDP), one of the key learning rules in biological system, can be realized by CMOS neurons and nanoscale memristor synapses.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/75835/1/josung_1.pd

Silicon Nanodevices

This book is a collection of scientific articles which brings research in Si nanodevices, device processing, and materials. The content is oriented to optoelectronics with a core in electronics and photonics. The issue of current technology developments in the nanodevices towards 3D integration and an emerging of the electronics and photonics as an ultimate goal in nanotechnology in the future is presented. The book contains a few review articles to update the knowledge in Si-based devices and followed by processing of advanced nano-scale transistors. Furthermore, material growth and manufacturing of several types of devices are presented. The subjects are carefully chosen to critically cover the scientific issues for scientists and doctoral students

Advanced light management concepts for perovskite photovoltaics

Um die rasante Zunahme der Treibhausgasemission zu bremsen und damit die globale Erderwärmung, ist ein schneller Umstieg von fossilen Brennstoffen auf erneuerbare Energien unabdingbar. In dieser Hinsicht spielt die Photovoltaik (PV) eine entscheidende Rolle, um eine effiziente Dekarbonisierung der globalen Stromerzeugung voranzutreiben. Dafür wird gegenwärtig sowohl an bestehender Silizium-PV, als auch an neuen PV-Technologien geforscht. Der prominenteste Kandidat unter den neuen Technologien sind die Perowskit-Solarzellen. Diese haben in den letzten 10 Jahren eine beispiellose Effizienzsteigerung durchlaufen und erzielen heute Rekordwirkungsgrade über 25%. Die rasche Entwicklung der Perowskit-basierten PV ist vor allem durch das Versprechen einer kostengünstigen, effizienten und skalierbaren Technologie motiviert. Sie gilt zum einen als Konkurrenz zur bestehenden Silizium-PV und zum anderen als Partner für die Anwendung in Perowskit/Silizium Tandem-PV. In dieser Hinsicht bietet die Perowskit-basierte Tandem-PV die Aussicht, den derzeitigen Rekordwirkungsgrad von Silizium (c-Si) Solarzellen (≈27%) und sogar die Shockley-Queisser-Grenze für Einfachsolarzellen (≈34%) zu übertreffen. Eine verbleibende Herausforderung, sowie ein aktuell stark untersuchtes Forschungsthema von Perowskit/c-Si-Tandemsolarzellen, ist ihre geringere Lichtausbeute im Vergleich zu konventionellen c-Si Solarzellen. Dies ist insbesondere auf zusätzlich erforderliche Funktionsschichten, wie die transparenten Elektroden, Ladungstransportschichten und Passivierungsschichten zurückzuführen, die gemeinsam zu Reflexionsverlusten und Verlusten durch parasitäre Absorption beitragen. Dies reduziert sowohl den Wirkungsgrad (PCE) als auch den Energieertrag (EY) der Tandem-Solarzelle. Um Reflexions- und Absorptionsverluste zu minimieren, ist ein fortschrittliches Lichtmanagement unerlässlich. Da sich die realistischen Einstrahlungsbedingungen stark von typischen Standardtestbedingungen unterscheiden (z.B. spektrale Variation und variabler Einfallswinkel des Sonnenlichts), ist es zwingend notwendig, PV-Module nicht nur für den PCE, sondern auch für den EY zu optimieren. Daher ist ein ausgeklügeltes Lichtmanagement nicht nur auf Tandem-Solarmodule beschränkt, sondern für jede Art von Solarmodul wichtig. In dieser Arbeit werden verschiedene Lichtmanagementkonzepte für die Perowskit-basierte-PV diskutiert und in Bezug auf den PCE und den jährlichen EY bewertet. In diesem Zusammenhang werden Mikrotexturen für eine verbesserte Lichteinkopplung an der Luft/Glas-Grenzfläche untersucht, was für alle PV-Technologien relevant ist. Die Mikrotexturen an der Vorderseite des Solarmoduls bieten die Möglichkeit, die Luft/Glas-Reflexion fast vollständig zu eliminieren und bei schrägen Einfallswinkeln (z.B. 80°) um ca. 80%rel zu reduzieren. Die experimentelle Realisierung zeigt die Erhöhung des PCE um 12%rel bzw. 5%rel für planare und texturierte Siliziumsolarzellen. Darüber hinaus werden Mikrotexturen auf Perowskit/c-Si-Tandem-Minimodulen realisiert, die den PCE um 10%rel verbessern. Aufgrund der ausgezeichneten Winkelstabilität der Mikrotexturen spiegelt sich die Verbesserung des PCE auch im EY wider, was durch Simulationen gezeigt wird, bei denen die Verbesserungen im EY die des PCE um 2%rel übertreffen. Zusätzlich zur ersten Grenzfläche jedes Solarmoduls werden die Reflexionsverluste an den vorderen halbtransparenten Indiumzinnoxid (ITO) Elektroden der Perowskit-Solarzellen untersucht. Mit Hilfe von nanotexturierten Glas/ITO-Grenzflächen können diese Verluste minimiert werden, was zu einem verbesserten Strom in der oberen Perowskit- und unteren c-Si-Solarzelle führt. Dies verbessert den Tandem-PCE um 2%rel. Darüber hinaus sind die nanotexturierten Elektroden winkelstabil und versprechen in den Simulationen eine Erhöhung des EY um 10%rel, was höher ist als die simulierte Verbesserung des PCE um 9%rel. Weitere nanophotonische Modifikationen der Absorberschicht der Perowskit-Solarzelle führen zu einer verbesserten Absorption in der Nähe der Bandlücke, indem das einfallende Licht in quasi-geführte Moden eingekoppelt wird. Simulationen zeigen, dass dies die Stromerzeugung in den Perowskit-Solarzellen um bis zu 6%rel verbessert. Erste experimentelle Ergebnisse demonstrieren eine Verbesserung um 2%rel. Darüber hinaus bieten die nanophotonischen Perowskit-Solarzellen eine einfache Möglichkeit, den um-weltschädlichen Bleigehalt in den Perowskit-Solarzellen bei gleichbleibendem Wirkungsgrad, um 30%rel zu verringern. Darüber hinaus verändert die nanophotonische Modifikation des Absorbers die Winkelabhängigkeit der Perowskit-Solarzellen nicht und führt zu den äquivalenten Verbesserungen des EY. Schließlich wird ein neuartiges Herstellungsverfahren für Perowskit-Solarzellen vorgestellt, dass eine einfache Laminierung der Perowskit-Solarzellen ermöglicht. Damit umgeht die Laminierung Inkompatibilitäten bei konventionellen Schichtabscheidungs-techniken und bietet somit mehr Flexibilität und Freiheit bei der Wahl der Ladungstransportmaterialien für die Perowskit-Solarzellenherstellung. Erste Prototypen zeigen eine ausgezeichnete Langzeit- und Temperaturstabilität der laminierten Perowskit-Solarzellen mit einem PCE über 14%. Das vorgestellte Laminierungskonzept bahnt damit den Weg für eine direkte Laminierung von Perowskit-Solarzellen auf die bestehende Siliziumtechnologie und hat so ein großes Potential für die aktuelle Perowskit-basierte Tandemforschung

Magnetic materials : fundamental synthesis of two-dimensional magnets and applications to neuromorphic computing

Two dimensional magnetic materials hold the promise of helping to achieve beyond CMOS computing tasks. 2D magnetic materials can be used in fabricating magnetic tunnel junctions with higher tunnel magnetoresistance which can then be applied to making new neuromorphic computing architectures primarily geared towards artificial intelligence and machine learning applications. In this work I summarize my synthesis and investigation of the properties of Cr₂C which belongs to the group of 2D transition metal carbides or nitrides called MXenes. Cr₂C has been predicted to have intrinsic half metallic ferromagnetic behaviors. These magnetic behaviors can be tuned based on the level of functionalization of the surface of the material. I show different parameters such as etchant, reaction temperature, and molar concentration that I have tuned in order to optimally derive Cr₂C from its parent MAX phase Cr₂AlC by removing the Al layer with a fluoride salt and hydrochloric acid. I also show how magnetic tunnel junctions (MTJs), which are two ferromagnetic layers with a tunnel barrier in between, can be used to make a synapse which is a neuromorphic computing primitive. The synapse circuit that I have proposed displays spike timing dependent plasticity which is an integral component of learning and memory in the brain. I show how different delay conditions between the presynaptic signal and the postsynaptic signal lead to currents of different magnitudes flowing through the ferromagnetic layer of the magnetic tunnel junction synapse. I also show how these currents move the domain wall both in micromagnetic simulation and using a domain wall MTJ Spice model that has been developed. I went on to wire four of these synapses together to observe the temporal dynamics of the system. My results show that the lower the delay between the presynaptic pulse and the postsynaptic pulse, the higher the current through the MTJ synapse and hence the larger the domain wall displacement. These studies pave the way for empirical understanding of the Cr₂C MXene, including its potential magnetic properties, as well as doing online machine learning classification tasks with arrays of magnetic synapsesElectrical and Computer Engineerin

Design Automation and Application for Emerging Reconfigurable Nanotechnologies

In the last few decades, two major phenomena have revolutionized the electronic industry – the ever-increasing dependence on electronic circuits and the Complementary Metal Oxide Semiconductor (CMOS) downscaling. These two phenomena have been complementing each other in a way that while electronics, in general, have demanded more computations per functional unit, CMOS downscaling has aptly supported such needs. However, while the computational demand is still rising exponentially, CMOS downscaling is reaching its physical limits. Hence, the need to explore viable emerging nanotechnologies is more imperative than ever. This thesis focuses on streamlining the existing design automation techniques for a class of emerging reconfigurable nanotechnologies. Transistors based on this technology exhibit duality in conduction, i.e. they can be configured dynamically either as a p-type or an n-type device on the application of an external bias. Owing to this dynamic reconfiguration, these transistors are also referred to as Reconfigurable Field-Effect Transistors (RFETs). Exploring and developing new technologies just like CMOS, require tackling two main challenges – first, design automation flow has to be modified to enable tailor- made circuit designs. Second, possible application opportunities should be explored where such technologies can outsmart the existing CMOS technologies. This thesis targets the above two objectives for emerging reconfigurable nanotechnologies by proposing approaches for enabling an Electronic Design Automation (EDA) flow for circuits based on RFETs and exploring hardware security as an application that exploits the transistor-level dynamic reconfiguration offered by this technology. This thesis explains the bottom-up approach adopted to propose a logic synthesis flow by identifying new logic gates and circuit design paradigms that can particularly exploit the dynamic reconfiguration offered by these novel nanotechnologies. This led to the subsequent need of finding natural Boolean logic abstraction for emerging reconfigurable nanotechnologies as it is shown that the existing abstraction of negative unate logic for CMOS technologies is sub-optimal for RFETs-based circuits. In this direction, it has been shown that duality in Boolean logic is a natural abstraction for this technology and can truly represent the duality in conduction offered by individual transistors. Finding this abstraction paved the way for defining suitable primitives and proposing various algorithms for logic synthesis and technology mapping. The following step is to explore compatible physical synthesis flow for emerging reconfigurable nanotechnologies. Using silicon nanowire-based RFETs, .lef and .lib files have been provided which can provide an end-to-end flow to generate .GDSII file for circuits exclusively based on RFETs. Additionally, new approaches have been explored to improve placement and routing for circuits based on reconfigurable nanotechnologies. It has been demonstrated how these approaches led to superior results as compared to the native flow meant for CMOS. Lastly, the unique property of transistor-level reconfiguration offered by RFETs is utilized to implement efficient Intellectual Property (IP) protection schemes against adversarial attacks. The ability to control the conduction of individual transistors can be argued as one of the impactful features of this technology and suitably fits into the paradigm of security measures. Prior security schemes based on CMOS technology often come with large overheads in terms of area, power, and delay. In contrast, RFETs-based hardware security measures such as logic locking, split manufacturing, etc. proposed in this thesis, demonstrate affordable security solutions with low overheads. Overall, this thesis lays a strong foundation for the two main objectives – design automation, and hardware security as an application, to push emerging reconfigurable nanotechnologies for commercial integration. Additionally, contributions done in this thesis are made available under open-source licenses so as to foster new research directions and collaborations.:Abstract List of Figures List of Tables 1 Introduction 1.1 What are emerging reconfigurable nanotechnologies? 1.2 Why does this technology look so promising? 1.3 Electronics Design Automation 1.4 The game of see-saw: key challenges vs benefits for emerging reconfigurable nanotechnologies 1.4.1 Abstracting ambipolarity in logic gate designs 1.4.2 Enabling electronic design automation for RFETs 1.4.3 Enhanced functionality: a suitable fit for hardware security applications 1.5 Research questions 1.6 Entire RFET-centric EDA Flow 1.7 Key Contributions and Thesis Organization 2 Preliminaries 2.1 Reconfigurable Nanotechnology 2.1.1 1D devices 2.1.2 2D devices 2.1.3 Factors favoring circuit-flexibility 2.2 Feasibility aspects of RFET technology 2.3 Logic Synthesis Preliminaries 2.3.1 Circuit Model 2.3.2 Boolean Algebra 2.3.3 Monotone Function and the property of Unateness 2.3.4 Logic Representations 3 Exploring Circuit Design Topologies for RFETs 3.1 Contributions 3.2 Organization 3.3 Related Works 3.4 Exploring design topologies for combinational circuits: functionality-enhanced logic gates 3.4.1 List of Combinational Functionality-Enhanced Logic Gates based on RFETs 3.4.2 Estimation of gate delay using the logical effort theory 3.5 Invariable design of Inverters 3.6 Sequential Circuits 3.6.1 Dual edge-triggered TSPC-based D-flip flop 3.6.2 Exploiting RFET’s ambipolarity for metastability 3.7 Evaluations 3.7.1 Evaluation of combinational logic gates 3.7.2 Novel design of 1-bit ALU 3.7.3 Comparison of the sequential circuit with an equivalent CMOS-based design 3.8 Concluding remarks 4 Standard Cells and Technology Mapping 4.1 Contributions 4.2 Organization 4.3 Related Work 4.4 Standard cells based on RFETs 4.4.1 Interchangeable Pull-Up and Pull-Down Networks 4.4.2 Reconfigurable Truth-Table 4.5 Distilling standard cells 4.6 HOF-based Technology Mapping Flow for RFETs-based circuits 4.6.1 Area adjustments through inverter sharings 4.6.2 Technology Mapping Flow 4.6.3 Realizing Parameters For The Generic Library 4.6.4 Defining RFETs-based Genlib for HOF-based mapping 4.7 Experiments 4.7.1 Experiment 1: Distilling standard-cells from a benchmark suite 4.7.2 Experiment 2A: HOF-based mapping . 4.7.3 Experiment 2B: Using the distilled standard-cells during mapping 4.8 Concluding Remarks 5 Logic Synthesis with XOR-Majority Graphs 5.1 Contributions 5.2 Organization 5.3 Motivation 5.4 Background and Preliminaries 5.4.1 Terminologies 5.4.2 Self-duality in NPN classes 5.4.3 Majority logic synthesis 5.4.4 Earlier work on XMG 5.4.5 Classification of Boolean functions 5.5 Preserving Self-Duality 5.5.1 During logic synthesis 5.5.2 During versatile technology mapping 5.6 Advanced Logic synthesis techniques 5.6.1 XMG resubstitution 5.6.2 Exact XMG rewriting 5.7 Logic representation-agnostic Mapping 5.7.1 Versatile Mapper 5.7.2 Support of supergates 5.8 Creating Self-dual Benchmarks 5.9 Experiments 5.9.1 XMG-based Flow 5.9.2 Experimental Setup 5.9.3 Synthetic self-dual benchmarks 5.9.4 Cryptographic benchmark suite 5.10 Concluding remarks and future research directions 6 Physical synthesis flow and liberty generation 6.1 Contributions 6.2 Organization 6.3 Background and Related Work 6.3.1 Related Works 6.3.2 Motivation 6.4 Silicon Nanowire Reconfigurable Transistors 6.5 Layouts for Logic Gates 6.5.1 Layouts for Static Functional Logic Gates 6.5.2 Layout for Reconfigurable Logic Gate 6.6 Table Model for Silicon Nanowire RFETs 6.7 Exploring Approaches for Physical Synthesis 6.7.1 Using the Standard Place & Route Flow 6.7.2 Open-source Flow 6.7.3 Concept of Driver Cells 6.7.4 Native Approach 6.7.5 Island-based Approach 6.7.6 Utilization Factor 6.7.7 Placement of the Island on the Chip 6.8 Experiments 6.8.1 Preliminary comparison with CMOS technology 6.8.2 Evaluating different physical synthesis approaches 6.9 Results and discussions 6.9.1 Parameters Which Affect The Area 6.9.2 Use of Germanium Nanowires Channels 6.10 Concluding Remarks 7 Polymporphic Primitives for Hardware Security 7.1 Contributions 7.2 Organization 7.3 The Shift To Explore Emerging Technologies For Security 7.4 Background 7.4.1 IP protection schemes 7.4.2 Preliminaries 7.5 Security Promises 7.5.1 RFETs for logic locking (transistor-level locking) 7.5.2 RFETs for split manufacturing 7.6 Security Vulnerabilities 7.6.1 Realization of short-circuit and open-circuit scenarios in an RFET-based inverter 7.6.2 Circuit evaluation on sub-circuits 7.6.3 Reliability concerns: A consequence of short-circuit scenario 7.6.4 Implication of the proposed security vulnerability 7.7 Analytical Evaluation 7.7.1 Investigating the security promises 7.7.2 Investigating the security vulnerabilities 7.8 Concluding remarks and future research directions 8 Conclusion 8.1 Concluding Remarks 8.2 Directions for Future Work Appendices A Distilling standard-cells B RFETs-based Genlib C Layout Extraction File (.lef) for Silicon Nanowire-based RFET D Liberty (.lib) file for Silicon Nanowire-based RFET