A Complementary Resistive Switch-based Crossbar Array Adder

Redox-based resistive switching devices (ReRAM) are an emerging class of non-volatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic sneak currents are efficiently avoided. However, until now the CRS-based logic-in-memory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti et al.Comment: 12 pages, accepted for IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), issue on Computing in Emerging Technologie

Asymptotic Stability and Asymptotic Synchronization of Memristive Regulatory-Type Networks

Memristive regulatory-type networks are recently emerging as a potential successor to traditional complementary resistive switch models. Qualitative analysis is useful in designing and synthesizing memristive regulatory-type networks. In this paper, we propose several succinct criteria to ensure global asymptotic stability and global asymptotic synchronization for a general class of memristive regulatory-type networks. The experimental simulations also show the performance of theoretical results

전자 장치 내 국부적 전계 향상을 위한 나노 구조체

학위논문(박사) -- 서울대학교대학원 : 공과대학 화학생물공학부, 2021.8. 조재영.The goal of this dissertation is to investigate effect of nanostructures for local electric field enhancement in electronic devices and to provide experimental and theoretical bases for their practical use. Resistive random access memory (RRAM) is a data storage device that can be modulated its resistance states by external electrical stimuli. The electric field generated by the applied potential difference between the two electrodes acts as the driving force to switch the resistance states, so controlling the electric field within the device can lead to improved operational performance and reliability of the device. Even though considerable progress has been made through significant efforts to control the electric field within the device, selectively enhancing the electric field in the intended position for stable and uniform resistive switching behavior is still challenging. Engineered metal structures in the RRAM can efficiently manipulate the electric field. As the radius of the metal structures decreases, the charge density increases, generating electric field enhancements in confined region. To minimize the radius of the metal structure and thus to greatly increase the electric field in a local area, we introduced a nanoscale metal structure into the RRAM. First, pyramid-structured metal electrode with a sharp tip was used to achieve a tip-enhanced electric field, and the effect of the enhanced electric field on the resistive switching behaviors of the device was investigated. Based on numerical simulation and experimental results, we confirmed that pyramidal electrode with a tip radius of tens of nanometers can selectively enhance the electric field at the tip. The tip-enhanced electric field can facilitate the thermochemical reaction in transition metal oxide-based RRAMs and efficiency of charge injection and transport in organic-based RRAMs, as well as provide position selectivity during formation of conductive filament. The resulting RRAM exhibited reliable resistive switching behavior and highly improved device performance compared with conventional RRAM with planar electrode. As another approach to enhance the electric field within the resistive switching layer, we prepared spherical nanostructures via self-assembled block copolymer (BCP)/metal compound micelles. BCP and metal precursors were dissolved in aqueous media for use as BCP/metal compound micelles. These micelles were used as complementary resistive switch (CRS) layers of the memory device and the mechanism of CRS behavior was investigated. The spherical metal nanostructures can improve the electric fields, promoting a resistive switching mechanism based on electrochemical metallization. The resulting CRS memory exhibited reliable resistive switching behavior with four distinct threshold voltages in both cycle-to-cycle and cell-to-cell tests. Also, the conduction and resistive switching mechanism are experimentally demonstrated through the the analysis of the current–voltage data plot and detemination of the temperature coefficient of resistance. Overall, we pursued efficient engineering of metal nanostructures capable of manipulating electric fields for improving the operational performance and reliability of memory devices. There is no doubt that the commercialized RRAM will become popular in the near future after overcoming all the challenges of RRAM through continuous interest and research. We believe that these results will not only contribute to the significant advancement of all electronic devices, including RRAM, but will also help promote research activities in the electronic device field.본 논문의 목적은 나노 구조체를 통한 전자 장치 내 국부적 전계 향상 효과를 조사하고, 이의 실제 사용을 위한 실험 및 이론적 기반을 제공하는 것이다. 저항변화메모리 (resistive random access memory) 는 외부 전기 자극에 의해 저항 상태를 변화 시킬 수 있는 데이터 저장 장치이다. 두 전극 사이에 인가된 전위차에 의해 생성된 전기장은 저항 상태를 전환시키는 구동력으로써 작용하므로, 전자 장치 내에서 전기장을 제어하면 장치의 성능과 신뢰성을 향상시킬 수 있다. 장치 내에서 전기장을 제어하려는 많은 노력을 통해 상당한 진전이 있었지만, 안정적이고 균일한 저항 변화 거동을 위해 의도된 위치에서 전기장을 선택적으로 향상시키는 일은 아직 도전적 과제이다. 구조화된 금속을 저항변화메모리에 접목시킴으로써 전기장을 효율적으로 조작할 수 있다. 금속 구조체의 반경이 감소함에 따라 전하 밀도가 증가하여 국부적 영역에서 전기장이 향상된다. 이 논문에서는 금속 구조체의 반경을 최소화하여 국부적으로 전기장을 크게 향상시키기 위해 저항변화메모리에 나노스케일의 금속 구조체를 도입하였다. 첫 번째로, 팁 강화 (tip-enhanced) 전기장 효과를 달성하기 위해 날카로운 팁을 가지는 피라미드 금속 구조체를 전극으로 사용하였으며, 강화된 전기장이 소자의 저항 변화 거동에 미치는 영향을 조사하였다. 유한요소모델링과 실험결과를 바탕으로, 수십 나노 미터의 팁 반경을 가지는 피라미드 구조체 전극이 팁 부근에서 전기장을 국소적으로 향상시킬 수 있음을 확인하였다. 팁 강화 전기장은 전이 금속 산화물-기반 저항변화메모리에서 열화학 (thermochemical) 반응을 촉진시키고 유기-기반 저항변화메모리에서 전하 주입 (charge injection) 및 수송 (transport) 효율성을 향상시킬 뿐 아니라, 선택적인 위치에서만 전도성 필라멘트 (conductive filament)를 형성시킬 수 있었다. 그 결과 피라미드 구조체 저항변화메모리는 종래의 평판 구조체 저항변화메모리에 비해 안정적인 저항 변화 거동과 향상된 장치 성능을 보여주었다. 저항 변화 층 내의 전기장을 향상시키기 위한 또 다른 접근법으로, 자기조립 (self-assembled)된 블록공중합체 (block copolymer)/금속 복합체 미셀 (micelle)을 이용하여 구형의 나노구조체를 소자의 중간층으로 도입하였다. 블록공중합체 및 금속전구체를 복합체 미셀로 사용하기 위해 선택적 용매에 용해시켰다. 해당 미셀을 메모리 소자의 상보적 저항 변화 (complementary resistive switch) 층으로 사용하였으며, 상보적 저항 변화 거동의 메커니즘을 조사하였다. 구형의 금속 나노구조체는 전기장을 향상시켜 전기화학적 금속화 (electrochemical metallization)에 기반한 저항 변화 메커니즘을 촉진시킬 수 있었다. 그 결과 상보적 저항 변화 메모리는 사이클 및 셀간 반복 시험 모두에서 4개의 임계 전압으로 안정적인 저항 변화 동작을 나타내었다. 또한 전류-전압 자료 플롯 (plot) 분석과 저항의 온도 계수 결정을 통해 장치의 전도 및 저항 변화 메커니즘을 실험적으로 입증하였다. 전반적으로 본 논문에서는 장치 내 전기장을 증폭시킬 수 있는 금속 나노구조체의 효율적인 엔지니어링을 통해 메모리 장치의 성능과 신뢰성 향상을 추구하였다. 지속적인 관심과 연구를 통해 저항변화메모리의 모든 과제를 극복한 후, 상용화된 저항변화메모리가 가까운 미래에 대중화될 것임을 믿어 의심치 않는다. 우리는 이 결과가 저항변화메모리를 포함한 모든 전자 장치의 획기적인 발전에 기여할 뿐만 아니라 전자 장치 분야의 연구 활동을 촉진하는 데에도 도움이 될 것이라고 믿는다.Chapter 1. Introduction 1 1.1. Background 1 1.1.1. Necessity of new memory devices 1 1.1.2. Resistive random access memory 2 1.2. Motivation 4 1.3. Dissertation Overview 6 1.4. References 9 Chapter 2. Tip-Enhanced Electric Field-Driven Efficient Charge Injection and Transport in Organic Material-Based Resistive Memories 19 2.1. Introduction 21 2.2. Experimental 24 2.3. Results and Discussion 27 2.4. Conclusions 37 2.5. References 38 Chapter 3. Facilitation of the Thermochemical Mechanism in NiO-Based Resistive Switching Memories via Tip-Enhanced Electric Fields 52 3.1. Introduction 54 3.2. Experimental 57 3.3. Results and Discussion 60 3.4. Conclusions 66 3.5. References 67 Chapter 4. Facile Achievement of Complementary Resistive Switching Behaviors via Self-Assembled Block Copolymer Micelles 82 4.1. Introduction 83 4.2. Experimental 86 4.3. Results and Discussion 89 4.4. Conclusions 96 4.5. References 97 Chapter 5. Conclusion 109 Abstract in Korean 112박

Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices

Highly accurate and predictive models of resistive switching devices are needed to enable future memory and logic design. Widely used is the memristive modeling approach considering resistive switches as dynamical systems. Here we introduce three evaluation criteria for memristor models, checking for plausibility of the I-V characteristics, the presence of a sufficiently non-linearity of the switching kinetics, and the feasibility of predicting the behavior of two anti-serially connected devices correctly. We analyzed two classes of models: the first class comprises common linear memristor models and the second class widely used non-linear memristive models. The linear memristor models are based on Strukovs initial memristor model extended by different window functions, while the non-linear models include Picketts physics-based memristor model and models derived thereof. This study reveals lacking predictivity of the first class of models, independent of the applied window function. Only the physics-based model is able to fulfill most of the basic evaluation criteria.Comment: 9 pages; accepted for IEEE TCAS-

MADX: Memristors-As-Drivers for Crossbar logic

Memristors have the potential to not only replace conventional memory, but also to open up new design possibilities because they store 1s and 0s as resistances rather than voltages. A memristor architecture that has attracted interest for its versatility and ease of integration with existing CMOS technologies is the crossbar array. In this paper, I modify the MAD scheme to create the MADX scheme for performing basic logic operations within a crossbar array. Then, I compare this scheme against two of the most well-known schemes, MAGIC and IMPLY. In the case study of a full-adder, both a one-bit and an 8-bit version, the MADX scheme achieves lower latency and substantially lower area requirements than both MAGIC and IMPLY. This is because it is more flexible about storing output values than either, does not destroy input values unlike IMPLY, and has more basic operations. In particular, it has XOR, which neither IMPLY nor MAGIC have and is useful for additionPlan II Honors Progra

Experimental study of artificial neural networks using a digital memristor simulator

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.Peer ReviewedPostprint (author's final draft