Marine Thruster I/O Board Redesign, Prototyping, and Certification

For about 20 years, the company Marine Technologies have used a circuit board called the IOB, which controls input and output signals. The Input Output Board (IOB) uses a logic device to manage the different signals. For the last 20 years this has been an FPGA (Field Programmable Gate Arrays). The manufacture, design, and supply of IOB belonged to another company, but the time came for Marine Technologies to claim the ownership of the IOB and make a design of their own. This was a good opportunity to make design changes and the possibility of using microcontrollers instead of FPGAs became an interesting pursuit. Microcontrollers naturally are cheaper and easier to acquire and have become considerably advanced, making them a possible replacement candidate. This thesis explores the process of implementing a microcontroller with the new IOB design and having the product certified. The new IOB must fulfill Marine Technologies’ set of demands which require it to be functionally identical to the original; it also needs to fulfill the international sets of standards that amongst other things set the demands for environmental robustness and Electromagnetic Compatibility (EMC) performance. To meet this set of demands, I completed an analysis of the current I/O usage of Marine Technologies’ systems and reduced the amount of I/O available to match this actual usage. This proved that a microcontroller have enough resources to handle the actual required I/O load of Marine Technologies’ systems. In terms of EMC, the best one can do is to design a circuit board that follows design guidelines for EMC as closely as possible and test it when the prototype arrives. The number one rule for EMC minded design, is to allow return currents to flow directly under the outgoing signal trace, which is best achieved by having dedicated, proper, and unbroken power and ground planes, placed in the layers between the top and bottom layer of the PCB. The design of the new IOB, called MT-IOB-Mk3-Transit, was done by closely examining the design of the previous two FPGA based iterations of the IOB, called the MT-IOB-Mk1 and MT-IOB-Mk2. The IOB-Mk3-Transit uses elements from both boards, by looking at 20 years of field testing and usage, what works best and what does not, while at the same time considering how the new microcontroller fits within these elements. In most aspects the IOB-Mk3-Transit is a mosaic containing elements from both the IOB-Mk1 and the Mk2, which are known to function reliably for 20 years. During functional testing of the IOB-Mk3-Transit, the crucial functions were working well. The board was tested in a certification lab in Italy, and due to the board being designed with sub optimal EMC practice, we used two attempts in Italy before finally passing the EMC tests, requiring some research at home before travelling for the second attempt. The product was then certified, installed on a vessel and is now in use. Taking the lessons learned from the IOB-Mk3-Transit, the new iteration purely called the MT-IOB-Mk3 has been designed, following the stated EMC guidelines closely to improve performance, and correcting a few minor issues of the IOB-Mk3-Transit. This board has yet to be tested. In the end, the question of using a microcontroller instead of an FPGA to perform the duties of the IOB, is only partially answered. Yes, the microcontroller can perform all the required functions that the FPGA did, and it will be implemented as a part of the Marine Technologies environment for now, but long-term reliability is a question that can only be answered by long-term use and testing.Masteroppgave i fysikkPHYS399MAMN-PHY

Computing the fast Fourier transform on SIMD microprocessors

This thesis describes how to compute the fast Fourier transform (FFT) of a power-of-two length signal on single-instruction, multiple-data (SIMD) microprocessors faster than or very close to the speed of state of the art libraries such as FFTW (“Fastest Fourier Transform in the West”), SPIRAL and Intel Integrated Performance Primitives (IPP). The conjugate-pair algorithm has advantages in terms of memory bandwidth, and three implementations of this algorithm, which incorporate latency and spatial locality optimizations, are automatically vectorized at the algorithm level of abstraction. Performance results on 2- way, 4-way and 8-way SIMD machines show that the performance scales much better than FFTW or SPIRAL. The implementations presented in this thesis are compiled into a high-performance FFT library called SFFT (“Streaming Fast Fourier Trans- form”), and benchmarked against FFTW, SPIRAL, Intel IPP and Apple Accelerate on sixteen x86 machines and two ARM NEON machines, and shown to be, in many cases, faster than these state of the art libraries, but without having to perform extensive machine specific calibration, thus demonstrating that there are good heuristics for predicting the performance of the FFT on SIMD microprocessors (i.e., the need for empirical optimization may be overstated)

Investigation of general-purpose computing on graphics processing units and its application to the finite element analysis of electromagnetic problems

In this dissertation, the hardware and API architectures of GPUs are investigated, and the corresponding acceleration techniques are applied on the traditional frequency domain finite element method (FEM), the element-level time-domain methods, and the nonlinear discontinuous Galerkin method. First, the assembly and the solution phases of the FEM are parallelized and mapped onto the granular GPU processors. Efficient parallelization strategies for the finite element matrix assembly on a single GPU and on multiple GPUs are proposed. The parallelization strategies for the finite element matrix solution, in conjunction with parallelizable preconditioners are investigated to reduce the total solution time. Second, the element-level dual-field domain decomposition (DFDD-ELD) method is parallelized on GPU. The element-level algorithms treat each finite element as a subdomain, where the elements march the fields in time by exchanging fields and fluxes on the element boundary interfaces with the neighboring elements. The proposed parallelization framework is readily applicable to similar element-level algorithms, where the application to the discontinuous Galerkin time-domain (DGTD) methods show good acceleration results. Third, the element-level parallelization framework is further adapted to the acceleration of nonlinear DGTD algorithm, which has potential applications in the field of optics. The proposed nonlinear DGTD algorithm describes the third-order instantaneous nonlinear effect between the electromagnetic field and the medium permittivity. The Newton-Raphson method is incorporated to reduce the number of nonlinear iterations through its quadratic convergence. Various nonlinear examples are presented to show the different Kerr effects observed through the third-order nonlinearity. With the acceleration using MPI+GPU under large cluster environments, the solution times for the various linear and nonlinear examples are significantly reduced

Design and validation of a scalable Digital Wireless Channel Emulator using an FPGA computing cluster

A Digital Wireless Channel Emulator (DWCE) is a system that is capable of emulating the RF environment for a group of wireless devices. The use of digital wireless channel emulators with networking radios is hampered by the inability to efficiently scale a DWCE to a large number of nodes. If such a large scale digital wireless channel emulator were to exist, a significant amount of time and money could be saved by testing networking radios in a laboratory before running lengthy and costly field tests. By utilizing the repeatability of a laboratory environment it will be possible to investigate and solve issues more quickly and efficiently. This will enable the performance of the radios to be known with a high degree of certainty before they are brought to the field. This dissertation investigates the use of an FPGA cluster configured as a distributed system to provide the computational and network structure to scale a DWCE to support 1250 or more wireless devices. This number of wireless devices is approximately two orders of magnitude larger than any other documented system. In this dissertation, the term ”scale” used for a DWCE is defined as an increase of three key factors: number of wireless devices, signal bandwidth emulated, and the fidelity of the emulation. It is possible to make tradeoffs and reduce any one of these to increase the other two. This dissertation shows a DWCE that can increase all of these factors in an efficient manner and thoroughly investigates the fidelity of the emulation it produces

Performance of the CMS Tracker Optical Links and Future Upgrade Using Bandwidth Efficient Digital Modulation

The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) particle accelerator will begin operation in 2007. The innermost CMS subdetector, the Tracker, comprises ~10 million detector channels read out by ~40 000 analog optical links. The optoelectronic components have been designed to meet the stringent requirements of a high energy physics (HEP) experiment in terms of radiation hardness, low mass and low power. Extensive testing has been performed on the components and on complete optical links in test systems. Their functionality and performance in terms of gain, noise, linearity, bandwidth and radiation hardness is detailed. Particular emphasis is placed on the gain, which directly affects the dynamic range of the detector data. It has been possible to accurately predict the variation in gain that will be observed throughout the system. A simulation based on production test data showed that the average gain would be ~38% higher than the design target at the Tracker operating temperature of -10°C. Corrective action was taken to reduce the gains and recover the lost dynamic range by lowering the optical receiver's load resistor value from 100Ω to 62Ω. All links will have gains between 0.64 and 0.96V/V. The future iteration of CMS will be operated in an upgraded LHC requiring faster data readout. In order to preserve the large investments made for the current readout system, an upgrade path that involves reusing the existing optoelectronic components is considered. The applicability of Quadrature Amplitude Modulation (QAM) in a HEP readout system is examined. The method for calculating the data rate is presented, along with laboratory tests where QAM signals were transmitted over a Tracker optical link. The results show that 3-4Gbit/s would be possible if such a design can be implemented (over 10 times the equivalent data rate of the current analog links, 320Mbits/s).(Abridged version) The CMS experiment at the LHC will begin operation in 2007. The CMS Tracker sub-detector, comprises ~10 million detector channels read out by ~40 000 analog optical links. The optoelectronic components have been designed to meet the stringent requirements of a HEP experiment in terms of radiation hardness, low mass and low power. Extensive testing has been performed on the components and on complete optical links in test systems. Their functionality and performance in terms of gain, noise, linearity, bandwidth and radiation hardness is detailed. Particular emphasis is placed on the gain, which directly affects the dynamic range of the detector data. It has been possible to accurately predict the variation in gain that will be observed throughout the system. A simulation based on production test data showed that the average gain would be ~38% higher than the design target at the Tracker operating temperature of -10{\deg}C. Corrective action was taken to reduce the gains and recover the lost dynamic range by lowering the optical receiver's load resistor value from 100{\Omega} to 62{\Omega}. All links will have gains between 0.64 and 0.96V/V. The future iteration of CMS will be operated in an upgraded LHC requiring faster data readout. In order to preserve the large investments made for the current readout system, an upgrade path that involves reusing the existing optoelectronic components is considered. The applicability of Quadrature Amplitude Modulation (QAM) in a HEP readout system is examined. The method for calculating the data rate is presented, along with laboratory tests where QAM signals were transmitted over a Tracker optical link. The results show that 3-4Gbit/s would be possible if such a design can be implemented (over 10 times the equivalent data rate of the current analog links, 320Mbits/s)

Diseño de un Sub-Sistema de Cómputo Distribuido que permita implementar virtualización inalámbrica para gestionar recursos (Procesamiento, memoria, almacenamiento y dispositivos E/S) distribuidos en una Red Ad Hoc, mediante el modelo de pseudo Estado

Las redes de comunicaciones dinámicas estocásticas como las redes ad hoc, están inmersas en ecosistemas altamente distribuidos como lo es Internet, incluso es un medio para implementar tecnologías como Ciudades inteligentes, Internet de las Cosas (IoT), entre otros. Estos ambientes distribuidos donde la cantidad de recursos de cómputo disponibles, la calidad de servicio (QoS), y la naturaleza de servicios solicitados por los usuarios son factores determinantes en las interacciones hombremáquina/ máquina-máquina, requieren de una abstracción que permita identificar y definir las interacciones entre los miembros de estos sistemas para ejecutar las tareas distribuidas con el fin de obtener el servicio sin importar las limitaciones de los dispositivos, una forma de resolver este problema es la construcción de un sistema operativo virtualizado orientado a redes ad hoc, bajo premisas sociales como la justicia o la equidad, necesaria en estos ambientes computacionales cambiantes.Abstract: The dynamic stochastic communication networks such as ad hoc networks are immersed in highly dis- tributed ecosystems such as the Internet, it is even a means to implement technologies such as Smart Cities, Internet of Things (IoT), among others. These distributed environments where the amount of computing resources available, the quality of service (QoS), and the nature of services requested by users are determining factors in human-machine / machine-machine interactions, require an abstrac- tion to identify and define the interactions between the members of these systems to execute the distributed tasks in order to obtain the service regardless of the limitations of the devices, one way to solve this problem is the construction of a virtualized operating system oriented to ad hoc networks, under social premises such as justice or equity, necessary in these changing computational environ- mentsDoctorad