A 2 GHz Bandpass Analog to Digital Delta-sigma Modulator for CDMA Receivers with 79 DB Dynamic Range in 1.23 MHz Bandwidth

This paper presents the design of a second-order single-bit analog-to-digital continuous-time delta-sigma modulator that can be used in wireless CDMA receivers. The continuous-time delta-sigma modulator samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79-dB signal-to-noise ratio (SNR) over a 1.23-MHz bandwidth. The continuous-time delta-sigma modulator was fabricated in a 0.18- m 1-poly 6-metal, CMOS technology and has an active area of approximately 0.892 mm2 . The delta-sigma modulator\u27s critical performance specifications are derived from the CDMA receiver specifications

Accurate spectral test algorithms with relaxed instrumentation requirements

Spectral testing is widely used to test the dynamic linearity performance of Analog-to-Digital Converters (ADC) and waveform generators. Dynamic specifications for ADCs are very important in high speed applications such as digital communications, ultrasound imaging and instrumentation. With improvements in the performance of ADCs, it is becoming an expensive and challenging task to perform spectral testing using standard methods due to the requirement that the test instrumentation environment must satisfy several stringent conditions. In order to address these challenges and to decrease the test cost, in this dissertation, three new algorithms are proposed to perform accurate spectral testing of ADCs by relaxing three necessary conditions required for standard spectral testing methods. The testing is done using uniformly sampled points. The first method introduces a new fundamental identification and replacement (FIRE) method, which eliminates the requirement of coherent sampling when using the DFT for testing the spectral response of an ADC. The robustness and accuracy of the proposed FIRE method is verified using simulation and measurement results obtained with non-coherently sampled data. The second method, namely, the Fundamental Estimation, Removal and Residue Interpolation (FERARI) method, is proposed to eliminate the requirement of precise control over amplitude and frequency of the input signal to the ADC. This method can be used when the ADC output is both non-coherently sampled and clipped. Simulation and measurement results using the FERARI method with non-coherently sampled and clipped outputs of the ADC are used to validate this approach. A third spectral test method is proposed that simultaneously relaxes the conditions of using a spectrally pure input source and coherent sampling. Using this method, the spectral characteristics of a high resolution ADC can be accurately tested using a non-coherently sampled output obtained with a sinusoidal input signal that has significant and unknown levels of nonlinear distortion. Simulation results are presented that show the accuracy and robustness of the proposed method. Finally, the issue of metastability in comparators and Successive Approximation Register (SAR) ADCs is analyzed. The analysis of probability of metastability in SAR ADCs with and without using metastable detection circuits is provided. Using this analysis, it is shown that as the frequency of sampling clock increases, using a metastable detection circuit decreases the probability of metastability in SAR ADC

Study of voltage controlled oscillator based analog-to-digital converter

A voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This thesis analyzes the performance of VCO-based ADCs in the presence of non idealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. Further, the study involves the use of VCO based Dual-slope A/D converter and its behaviour under different input voltage level. Graph is plotted between output voltages of the integrator vs. time. Digital circuits like a bit-counter and logic circuits are used for operation mode. A normal VCO model is also done in MATLAB-simulink environment and studied under variable input frequency and corresponding output plots are view

S-35 Beta Irradiation of a Tin Strip in a State of Superconducting Geometrical Metastability

We report the first energy loss spectrum obtained with a geometrically metastable type I superconducting tin strip irradiated by the beta-emission of S-35. (Nucl. Instr. Meth. A, in press)Comment: Compressed PostScript (filename.ps.Z), 9 pages, 2 figure

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

On time, time synchronization and noise in time measurement systems

Time plays an important role in our modern lives. Especially having accurate time, which in turn depends on having clocks being synchronized to each other. This thesis is split into three distinct parts. The first part deals with the mathematical description of noise that is required to model clocks and electronics accurately. In particular we will address the problem that the generally used tools from signal theory fail for noise signals which are neither of finite energy nor periodic in nature. For this we will introduce a new function space based on the Pp-seminorm that is an extension of the Lp-norm for functions of potentially infinite energy but limited power. Using this new semi-norm we will modify the Fourier transform to work on signals from this P p-space. And last but not least, we will introduce, based on the above, a new mathematical model of noise that captures all the properties associated with 1/f -noise. In the second part, we will look at how noise propagates in a few classes of electronics, especially how the non-linear behavior of electronics leads to an amplification of noise and how it could be miti-gated. Lastly, in the third part we will look at one approach of fault-tolerant clock synchronization. After explaining its working principle and showing an implementation in an FPGA we will focus on meta-stability, the problems it can cause and how to handle them on two different circuit levels.Zeit spielt eine wichtige Rolle in unserem Leben. Insbesondere die Verfügbarkeit einer genauen Zeit. Welches wiederum davon abhängt, dass man Uhren hat die auf einander synchronisiert laufen. Diese Arbeit ist in drei Teile aufgeteilt: Im ersten Teil betrachten wir die mathematische Beschreibung von Rauschen um elektronische Systeme und Uhren korrekt beschreiben zu können. Im Besonderen betrachten wir die Probleme die die generell benutzten Methoden der Signalverarbeitung beim Umgang mit Rauschsignalen haben, die weder energiebegrenzt noch periodisch sind. Dafür erweitern wir den Funktionenraum der Lp-Norm auf leistungslimiterte Funktionene und führen die Pp-Halbnorm ein und modifizieren die Fouriertransformation zur Verwendung auf diesen Raum. Und letztlich führen wir ein neues mathematisches Model zur Beschreibung von Rauschen ein, welches alle üblicherweise angenommenen Eigenschaften gleichzeitig erfüllt. Im zweiten Teil analysieren wir wie sich einige Klassen von elektronischen Schaltungem im Bezug auf Rauschen verhalten. Insbesondere im Bezug auf das nicht-lineare Verhalten der elektronischen Elemente, welches zu einer Verstärkung des Rauschens führt. Im dritten Teil betrachten wir eine Möglichkeit um fehlertolerante Synchronization von Uhren zu erreichen. Nach einem Überblick über den verwendeten Algorithmus und wie dieser einem FPGA implementiert werden kann, schauen wir uns den Einfluss von Metastabilität an und wie dieser eingedämmt werden kann

Front End Electronics for Neutron- Gamma Spectrometer Device

abstract: With the natural resources of earth depleting very fast, the natural resources of other celestial bodies are considered a potential replacement. Thus, there has been rise of space missions constantly and with it the need of more sophisticated spectrometer devices has increased. The most important requirement in such an application is low area and power consumption. To save area, some scintillators have been developed that can resolve both neutrons and gamma events rather than traditional scintillators which can do only one of these and thus, the spacecraft needs two such devices. But with this development, the requirements out of the readout electronics has also increased which now need to discriminate between neutron and gamma events. This work presents a novel architecture for discriminating such events and compares the results with another approach developed by a partner company. The results show excellent potential in this approach for the neutron-gamma discrimination and the team at ASU is going to expand on this design and build up a working prototype for the complete spectrometer device.Dissertation/ThesisMasters Thesis Engineering 201

Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices

This thesis project involves the design and analysis of an 8-bit Successive Approximation Register (SAR) Analog to Digital Convertor (ADC), designed for low- power applications such as bio-medical implants. The sampling rate for this ADC is 500 KS/s. The power consumption for the whole SAR ADC system was measured to be 2.1 uW. The novelty of this project is the proposal of an extremely energy efficient comparator architecture. The result is the design of a final ADC with reasonable sampling speed, accuracy and low power consumption. In this project, all the different subsystems have been designed at the transistor level with 45 nm CMOS technology. The logical circuit was designed using Verilog language. It was then synthesized and integrated in the overall system