137 research outputs found
ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ ๊ธฐ๋ฐ ๊ธฐ์ค ์ฃผํ์๋ฅผ ์ฌ์ฉํ์ง ์๋ ํด๋ก ๋ฐ ๋ฐ์ดํฐ ๋ณต์ ํ๋ก์ ์ค๊ณ ๋ฐฉ๋ฒ๋ก
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ์ ๋๊ท .In this thesis, a design of a high-speed, power-efficient, wide-range clock and data recovery (CDR) without a reference clock is proposed. A frequency acquisition scheme using a stochastic frequency detector (SFD) based on the Alexander phase detector (PD) is utilized for the referenceless operation. Pat-tern histogram analysis is presented to analyze the frequency acquisition behavior of the SFD and verified by simulation. Based on the information obtained by pattern histogram analysis, SFD using autocovariance is proposed. With a direct-proportional path and a digital integral path, the proposed referenceless CDR achieves frequency lock at all measurable conditions, and the measured frequency acquisition time is within 7ฮผs. The prototype chip has been fabricated in a 40-nm CMOS process and occupies an active area of 0.032 mm2. The proposed referenceless CDR achieves the BER of less than 10-12 at 32 Gb/s and exhibits an energy efficiency of 1.15 pJ/b at 32 Gb/s with a 1.0 V supply.๋ณธ ๋
ผ๋ฌธ์ ๊ธฐ์ค ํด๋ญ์ด ์๋ ๊ณ ์, ์ ์ ๋ ฅ, ๊ด๋์ญ์ผ๋ก ๋์ํ๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก์ ์ค๊ณ๋ฅผ ์ ์ํ๋ค. ๊ธฐ์ค ํด๋ญ์ด ์๋ ๋์์ ์ํด์ ์๋ ์ฐ๋ ์์ ๊ฒ์ถ๊ธฐ์ ๊ธฐ๋ฐํ ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ๋ฅผ ์ฌ์ฉํ๋ ์ฃผํ์ ํ๋ ๋ฐฉ์์ด ์ฌ์ฉ๋๋ค. ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ์ ์ฃผํ์ ์ถ์ ์์์ ๋ถ์ํ๊ธฐ ์ํด ํจํด ํ์คํ ๊ทธ๋จ ๋ถ์ ๋ฐฉ๋ฒ๋ก ์ ์ ์ํ์๊ณ ์๋ฎฌ๋ ์ด์
์ ํตํด ๊ฒ์ฆํ์๋ค. ํจํด ํ์คํ ๊ทธ๋จ ๋ถ์์ ํตํด ์ป์ ์ ๋ณด๋ฅผ ๋ฐํ์ผ๋ก ์๊ธฐ๊ณต๋ถ์ฐ์ ์ด์ฉํ ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ๋ฅผ ์ ์ํ๋ค. ์ง์ ๋น๋ก ๊ฒฝ๋ก์ ๋์งํธ ์ ๋ถ ๊ฒฝ๋ก๋ฅผ ํตํด ์ ์๋ ๊ธฐ์ค ํด๋ญ์ด ์๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก๋ ๋ชจ๋ ์ธก์ ๊ฐ๋ฅํ ์กฐ๊ฑด์์ ์ฃผํ์ ์ ๊ธ์ ๋ฌ์ฑํ๋ ๋ฐ ์ฑ๊ณตํ์๊ณ , ๋ชจ๋ ๊ฒฝ์ฐ์์ ์ธก์ ๋ ์ฃผํ์ ์ถ์ ์๊ฐ์ 7ฮผs ์ด๋ด์ด๋ค. 40-nm CMOS ๊ณต์ ์ ์ด์ฉํ์ฌ ๋ง๋ค์ด์ง ์นฉ์ 0.032 mm2์ ๋ฉด์ ์ ์ฐจ์งํ๋ค. ์ ์ํ๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก๋ 32 Gb/s์ ์๋์์ ๋นํธ์๋ฌ์จ 10-12 ์ดํ๋ก ๋์ํ์๊ณ , ์๋์ง ํจ์จ์ 32Gb/s์ ์๋์์ 1.0V ๊ณต๊ธ์ ์์ ์ฌ์ฉํ์ฌ 1.15 pJ/b์ ๋ฌ์ฑํ์๋ค.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 13
CHAPTER 2 BACKGROUNDS 14
2.1 CLOCKING ARCHITECTURES IN SERIAL LINK INTERFACE 14
2.2 GENERAL CONSIDERATIONS FOR CLOCK AND DATA RECOVERY 24
2.2.1 OVERVIEW 24
2.2.2 JITTER 26
2.2.3 CDR JITTER CHARACTERISTICS 33
2.3 CDR ARCHITECTURES 39
2.3.1 PLL-BASED CDR โ WITH EXTERNAL REFERENCE CLOCK 39
2.3.2 DLL/PI-BASED CDR 44
2.3.3 PLL-BASED CDR โ WITHOUT EXTERNAL REFERENCE CLOCK 47
2.4 FREQUENCY ACQUISITION SCHEME 50
2.4.1 TYPICAL FREQUENCY DETECTORS 50
2.4.1.1 DIGITAL QUADRICORRELATOR FREQUENCY DETECTOR 50
2.4.1.2 ROTATIONAL FREQUENCY DETECTOR 54
2.4.2 PRIOR WORKS 56
CHAPTER 3 DESIGN OF THE REFERENCELESS CDR USING SFD 58
3.1 OVERVIEW 58
3.2 PROPOSED FREQUENCY DETECTOR 62
3.2.1 MOTIVATION 62
3.2.2 PATTERN HISTOGRAM ANALYSIS 68
3.2.3 INTRODUCTION OF AUTOCOVARIANCE TO STOCHASTIC FREQUENCY DETECTOR 75
3.3 CIRCUIT IMPLEMENTATION 83
3.3.1 IMPLEMENTATION OF THE PROPOSED REFERENCELESS CDR 83
3.3.2 CONTINUOUS-TIME LINEAR EQUALIZER (CTLE) 85
3.3.3 DIGITALLY-CONTROLLED OSCILLATOR (DCO) 87
3.4 MEASUREMENT RESULTS 89
CHAPTER 4 CONCLUSION 99
APPENDIX A DETAILED FREQUENCY ACQUISITION WAVEFORMS OF THE PROPOSED SFD 100
BIBLIOGRAPHY 108
์ด ๋ก 122๋ฐ
Design of High-Speed Power-Efficient Transmitter with Time-Based Equalization
๋ณธ ๋
ผ๋ฌธ์ ๊ณ ์, ์ ์ ๋ ฅ์ผ๋ก ๋์ํ๋ ์ ์ ์ก์ ๊ธฐ์ ์ค๊ณ์ ๋ํด ์ค๋ช
ํ๊ณ ์๋ค. ๋ถ๋ฆฌ๋์ง ์์ ์ถ๋ ฅ ๋๋ผ์ด๋ฒ๊ฐ ์๋ ์๋์ง ํจ์จ์ ์ธ ์ ์ ๋ชจ๋ ์ก์ ๊ธฐ๋ ์์ ์ง์ฐ ๋ถ์์ ๊ธฐ๋ฐ์ผ๋ก ์๊ฐ ์์ญ์์ ์ฑ๋ ์์ค์ ๋ณด์ํ๋ค. ์ง๋ ฌํ๋ ๋ฐ์ดํฐ ์คํธ๋ฆผ์ด ์๋ ์ก์ ํด๋ญ์ ์์์ ๋ณ์กฐํจ์ผ๋ก์จ ์ ์๋ ์ก์ ๊ธฐ๋ ๋ฐ์ดํฐ ์์กด์ ์งํฐ๋ฅผ ํฌ๊ฒ ์ค์ธ๋ค. ์ํ ์์ด ์คํ๋์ ์ ์ก๋ ๋ฐ์ดํฐ์ ์คํ ๊ธธ์ด์ ๋ฐ๋ผ ์ ๋ก ํฌ๋ก์ฑ ์๊ฐ ๋ณ๋์ ๋ณด์ํจ์ผ๋ก์จ ๊ฐ์ ๋๋ค. ์ ์๋ ๋ฐฉ์์ ํฐ ์ ํธ ๋ฐ ์ค์์นญ ์ ๋ ฅ์ ์๋นํ๋ ๋ง์ ๋๋ผ์ด๋ฒ ์ฌ๋ผ์ด์ค๋ฅผ ์ ๊ฑฐํจ์ผ๋ก์จ ๋๋ผ์ด๋ฒ ๋ณต์ก์ฑ์ ํฌ๊ฒ ์ค์ธ๋ค.
ํ๋กํ ํ์
์นฉ์ 28 nm CMOS ๊ณต์ ์ผ๋ก ์ ์๋์์ผ๋ฉฐ 0.045 mm2 ์ ์ค์ ๋ฉด์ ์ ์ฐจ์งํ๋ค. ์ธก์ ๋ ๊ฒฐ๊ณผ๋ ์ ์๋ ์ก์ ๊ธฐ๊ฐ 1.0 V ๊ณต๊ธ์์ 440 mVppd์ ์ถ๋ ฅ ์ค์์ผ๋ก 22 Gb/s์ ์๋์์ 0.95 pJ/b์ ์๋์ง ํจ์จ์ ๋ฌ์ฑํจ์ ๋ณด์ฌ์ค๋ค. ๋ํ ํผํฌ ๋ ํผํฌ ์งํฐ๋ 15.0 dB ์์ค์ ์ฑ๋์ ๋ํด ์ ์๋ ์์ ์ง์ฐ ๋ณด์์ ํตํด 22 Gb/s์ ์๋์์ 34 ps์์ 20 ps๋ก ๊ฐ์๋๋ค.In this thesis, a design of high-speed, power-efficient wireline transmitter is reported. An energy-efficient voltage-mode transmitter with an un-segmented output driver equalizes channel loss in the time-domain based on the phase de-lay analysis. By modulating the phase of the transmitting clock rather than the serialized data stream, the proposed transmitter significantly reduces the data-dependent jitter. The horizontal eye-opening is improved by compensating for the zero-crossing time variation dependent on the run-length of the transmitted data. The proposed scheme significantly reduces the driver complexity by elim-inating many driver slices that consume significant signaling and switching power. The prototype chip has been fabricated in a 28-nm CMOS process and occupies an active area of 0.045 mm2. The measured results show that the pro-posed transmitter achieves an energy efficiency of 0.95 pJ/b at 22 Gb/s with an output swing of 440 mVppd at 1.0 V supply. In addition, peak-to-peak jitter is reduced from 34 ps to 20 ps at 22 Gb/s with the proposed phase delay compen-sation over the channel with a 15.0 dB loss.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 4
CHAPTER 2 BACKGROUNDS 5
2.1 OVERVIEW 5
2.2 FEED-FORWARD EQUALIZATION 7
2.2.1 AMPLITUDE-DOMAIN EQUALIZATION 7
2.2.2 PHASE-DOMAIN EQUALIZATION 12
2.2.3 PULSE-WIDTH MODULATION 18
2.3 ADAPTIVE FEED-FORWARD EQUALIZATION 21
2.3.1 AMPLITUDE-DOMAIN EQUALIZATION 21
2.3.2 PULSE-WIDTH MODULATION 24
CHAPTER 3 DESIGN OF THE TIME-BASED FEED-FORWARD EQUALIZATION OF THE TRANSMITTER 26
3.1 OVERVIEW 26
3.2 BASIC CONCEPT OF TIME-BASED FFE 28
3.2.1 ZERO-CROSSING TIME 28
3.2.2 PHASE DELAY 32
3.2.3 FINDING THE OPTIMUM COEFFICIENT 39
3.2.4 COMPARISON WITH CONVENTIONAL FFE 43
3.3 ADAPTIVE TIME-BASED FFE 50
3.3.1 OVERVIEW 50
3.3.2 BEHAVIORAL MODELING 51
3.3.3 SIMULATION RESULTS 53
3.4 TRANSMITTER IMPLEMENTATION 60
3.4.1 OVERVIEW 60
3.4.2 PHASE MODULATION 62
3.4.3 SERIALIZER AND CLOCK PATH 67
CHAPTER 4 MEASUREMENT 71
4.1 OVERVIEW 71
4.2 EYE DIAGRAM 76
4.3 POWER CONSUMPTION 81
CHAPTER 5 CONCLUSION 84
BIBLIOGRAPHY 86
์ด ๋ก 92๋ฐ
Energy-efficiency improvements for optical access
This article discusses novel approaches to improve energy efficiency of different optical access technologies, including time division multiplexing passive optical network (TDM-PON), time and wavelength division multiplexing PON (TWDM-PON), point-to-point (PTP) access network, wavelength division multiplexing PON (WDM-PON), and orthogonal frequency division multiple access PON (OFDMA-PON). These approaches include cyclic sleep mode, energy-efficient bit interleaving protocol, power reduction at component level, or frequency band selection. Depending on the target optical access technology, one or a combination of different approaches can be applied
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A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices
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Design of Power-Efficient Optical Transceivers and Design of High-Linearity Wireless Wideband Receivers
The combination of silicon photonics and advanced heterogeneous integration is promising for next-generation disaggregated data centers that demand large scale, high throughput, and low power. In this dissertation, we discuss the design and theory of power-efficient optical transceivers with System-in-Package (SiP) 2.5D integration. Combining prior arts and proposed circuit techniques, a receiver chip and a transmitter chip including two 10 Gb/s data channels and one 2.5 GHz clocking channel are designed and implemented in 28 nm CMOS technology.
An innovative transimpedance amplifier (TIA) and a single-ended to differential (S2D) converter are proposed and analyzed for a low-voltage high-sensitivity receiver; a four-to-one serializer, programmable output drivers, AC coupling units, and custom pads are implemented in a low-power transmitter; an improved quadrature locked loop (QLL) is employed to generate accurate quadrature clocks. In addition, we present an analysis for inverter-based shunt-feedback TIA to explicitly depict the trade-off among sensitivity, data rate, and power consumption. At last, the research on CDR-basedโ clocking schemes for optical links is also discussed. We introduce prior arts and propose a power-efficient clocking scheme based on an injection-locked phase rotator. Next, we analyze injection-locked ring oscillators (ILROs) that have been widely used for quadrature clock generators (QCGs) in multi-lane optical or wireline transceivers due to their low power, low area, and technology scalability. The asymmetrical or partial injection locking from 2 phases to 4 phases results in imbalances in amplitude and phase. We propose a modified frequency-domain analysis to provide intuitive insight into the performance design trade-offs. The analysis is validated by comparing analytical predictions with simulations for an ILRO-based QCG in 28 nm CMOS technology.
This dissertation also discusses the design of high-linearity wireless wideband receivers. An out-of-band (OB) IM3 cancellation technique is proposed and analyzed. By exploiting a baseband auxiliary path (AP) with a high-pass feature, the in-band (IB) desired signal and out-of-band interferers are split. OB third-order intermodulation products (IM3) are reconstructed in the AP and cancelled in the baseband (BB). A 0.5-2.5 GHz frequency-translational noise-cancelling (FTNC) receiver is implemented in 65nm CMOS to demonstrate the proposed approach. It consumes 36 mW without cancellation at 1 GHz LO frequency and 1.2 V supply, and it achieves 8.8 MHz baseband bandwidth, 40dB gain, 3.3dB NF, 5dBm OB IIP3, and โ6.5dBm OB B1dB. After IM3 cancellation, the effective OB-IIP3 increases to 32.5 dBm with an extra 34 mW for narrow-band interferers (two tones). For wideband interferers, 18.8 dB cancellation is demonstrated over 10 MHz with two โ15 dBm modulated interferers. The local oscillator (LO) leakage is โ92 dBm and โ88 dB at 1 GHz and 2 GHz LO respectively. In summary, this technique achieves both high OB linearity and good LO isolation
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Energy-efficient clock generation for communication and computing systems using injection locking
The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of the ring oscillator, enable a fast startup and conveniently generate multiple time-interleaved phases.
A quasi-linear model of injection-locked ring oscillator (ILRO) is utilized to mathematically formulate the frequency and time domain characteristics of the system, as well as the phase noise shaping and jitter tracking behavior. The settling behavior of ILRO is also exploited and shows a strong dependence on the locking range and the initial phase difference of the injected and the resultant oscillation signals.
A forwarded-clock synchronization based on injection locking is designed for a 10 Gb/s photonic interconnect according to the specific features of optical links. A single clock recovery can be used for all the four channels, resulting in a large amount of power and area saving. The applications of sub-harmonic and super-harmonic injection locking in wireless communications for frequency multiplying and division are also discussed
๋์ญํญ ์ฆ๋ ๊ธฐ์ ์ ์ด์ฉํ ์ ๋ ฅ ํจ์จ์ ๊ณ ์ ์ก์ ์์คํ ์ค๊ณ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022.2. ์ ๋๊ท .The high-speed interconnect at the datacenter is being more crucial as 400 Gb Ethernet standards are developed. At the high data rate, channel loss re-quires bandwidth extension techniques for transmitters, even for short-reach channels. On the other hand, as the importance of east-to-west connection is rising, the data center architectures are switching to spine-leaf from traditional ones. In this trend, the number of short-reach optical interconnect is expected to be dominant. The vertical-cavity surface-emitting laser (VCSEL) is a com-monly used optical modulator for short-reach interconnect. However, since VCSEL has low bandwidth and nonlinearity, the optical transmitter also needs bandwidth-increasing techniques. Additionally, the power consumption of data centers reaches a point of concern to affect climate change. Therefore, this the-sis focuses on high-speed, power-efficient transmitters for data center applica-tions. Before the presenting circuit design, bandwidth extension techniques such as fractionally-spaced feed-forward equalizer (FFE), on-chip transmission line, inductive peaking, and T-coil are mathematically analyzed for their effec-tiveness.
For the first chip, a power and area-efficient pulse-amplitude modulation 4 (PAM-4) transmitter using 3-tap FFE based on a slow-wave transmission line is presented. A passive delay line is adopted for generating an equalizer tap to overcome the high clocking power consumption. The transmission line achieves a high slow-wave factor of 15 with double floating metal shields around the differential coplanar waveguide. The transmitter includes 4:1 multi-plexers (MUXs) and a quadrature clock generator for high-speed data genera-tion in a quarter-rate system. The 4:1 MUX utilizes a 2-UI pulse generator, and the input configuration is determined by qualitative analysis. The chip is fabri-cated in 65 nm CMOS technology and occupies an area of 0.151 mm2. The proposed transmitter system exhibits an energy efficiency of 3.03 pJ/b at the data rate of 48 Gb/s with PAM-4 signaling.
The second chip presents a power-efficient PAM-4 VCSEL transmitter using 3-tap FFE and negative-k T-coil. The phase interpolators (PIs) generate frac-tionally-spaced FFE tap and correct quadrature phase error. The PAM-4 com-bining 8:1 MUX is proposed rather than combining at output driver with double 4:1 MUXs to reduce serializing power consumption. T-coils at the internal and output node increase the bandwidth and remove inter-symbol interference (ISI). The negative-k T-coil at the output network increases the bandwidth 1.61 times than without T-coil. The VCSEL driver is placed on the high VSS domain for anode driving and power reduction. The chip is fabricated in 40 nm CMOS technology. The proposed VCSEL transmitter operates up to 48 Gb/s NRZ and 64 Gb/s PAM-4 with the power efficiency of 3.03 pJ/b and 2.09 pJ/b, respec-tively.400Gb ์ด๋๋ท ํ์ค์ด ๊ฐ๋ฐ๋จ์ ๋ฐ๋ผ ๋ฐ์ดํฐ ์ผํฐ์ ๊ณ ์ ์ํธ ์ฐ๊ฒฐ์ด ๋์ฑ ์ค์ํด์ง๊ณ ์๋ค. ๋์ ๋ฐ์ดํฐ ์๋์์์ ์ฑ๋ ์์ค์ ์ํด ๋จ๊ฑฐ๋ฆฌ ์ฑ๋์ ๊ฒฝ์ฐ์๋ ์ก์ ๊ธฐ์ ๋ํ ๋์ญํญ ํ์ฅ ๊ธฐ์ ์ด ํ์ํ๋ค. ํํธ, ๋ฐ์ดํฐ ์ผํฐ ๋ด ๋-์ ์ฐ๊ฒฐ์ ์ค์์ฑ์ด ๋์์ง๋ฉด์ ๋ฐ์ดํฐ ์ผํฐ ์ํคํ
์ฒ๊ฐ ๊ธฐ์กด์ ์ํคํ
์ฒ์์ ์คํ์ธ-๋ฆฌํ๋ก ์ ํ๋๊ณ ์๋ค. ์ด๋ฌํ ์ถ์ธ์์ ๋จ๊ฑฐ๋ฆฌ ๊ดํ ์ธํฐ์ปค๋ฅํธ์ ์๊ฐ ์ ์ฐจ ์ฐ์ธํด์ง ๊ฒ์ผ๋ก ์์๋๋ค. ์์ง ์บ๋นํฐ ํ๋ฉด ๋ฐฉ์ถ ๋ ์ด์ (VCSEL)๋ ์ผ๋ฐ์ ์ผ๋ก ๋จ๊ฑฐ๋ฆฌ ์ํธ ์ฐ๊ฒฐ์ ์ํด ์ฌ์ฉ๋๋ ๊ดํ ๋ชจ๋๋ ์ดํฐ์ด๋ค. VCSEL์ ๋ฎ์ ๋์ญํญ๊ณผ ๋น์ ํ์ฑ์ ๊ฐ์ง๊ณ ์๊ธฐ ๋๋ฌธ์, ๊ด ์ก์ ๊ธฐ๋ ๋์ญํญ ์ฆ๊ฐ ๊ธฐ์ ์ ํ์๋ก ํ๋ค. ๋ํ, ๋ฐ์ดํฐ ์ผํฐ์ ์ ๋ ฅ ์๋น๋ ๊ธฐํ ๋ณํ์ ์ํฅ์ ๋ฏธ์น ์ ์๋ ์ฐ๋ ค ์ง์ ์ ๋๋ฌํ๋ค. ๋ฐ๋ผ์, ๋ณธ ๋
ผ๋ฌธ์ ๋ฐ์ดํฐ ์ผํฐ ์์ฉ์ ์ํ ๊ณ ์ ์ ๋ ฅ ํจ์จ์ ์ธ ์ก์ ๊ธฐ์ ์ด์ ์ ๋ง์ถ๊ณ ์๋ค. ํ๋ก ์ค๊ณ๋ฅผ ์ ์ํ๊ธฐ ์ ์, ๋ถ๋ถ ๊ฐ๊ฒฉ ํผ๋-ํฌ์๋ ์ดํ๋ผ์ด์ (FFE), ์จ์นฉ ์ ์ก์ ๋ก, ์ธ๋ํฐ, T-์ฝ์ผ๊ณผ ๊ฐ์ ๋์ญํญ ํ์ฅ ๊ธฐ์ ์ ์ํ์ ์ผ๋ก ๋ถ์ํ๋ค.
์ฒซ ๋ฒ์งธ ์นฉ์ ์ ์ํ ์ ์ก์ ๋ก๋ฅผ ๊ธฐ๋ฐ์ผ๋ก ํ 3-ํญ FFE๋ฅผ ์ฌ์ฉํ๋ ์ ๋ ฅ ๋ฐ ๋ฉด์ ํจ์จ์ ์ธ ํ์ค-์งํญ-๋ณ์กฐ 4(PAM-4) ์ก์ ๊ธฐ๋ฅผ ์ ์ํ๋ค. ๋์ ํด๋ญ ์ ๋ ฅ ์๋น๋ฅผ ๊ทน๋ณตํ๊ธฐ ์ํด ์ดํ๋ผ์ด์ ํญ ์์ฑ์ ์ํด ์๋์์ ์ง์ฐ ๋ผ์ธ์ ์ฑํํ๋ค. ์ ์ก ๋ผ์ธ์ ์ฐจ๋ ๋์ผํ๋ฉด๋ํ๊ด ์ฃผ์์ ์ด์ค ํ๋กํ
๊ธ์ ์ฐจํ๋ฅผ ์ฌ์ฉํ์ฌ 15์ ๋์ ์ ๋ฌ์๋ ๊ฐ์ ๋ฅผ ๋ฌ์ฑํ๋ค. ์ก์ ๊ธฐ์๋ 4:1 ๋ฉํฐํ๋ ์(MUX)์ 4-์์ ํด๋ญ ์์ฑ๊ธฐ๊ฐ ํฌํจ๋์ด ์๋ค. 4:1 MUX๋ 2-UI ํ์ค ๋ฐ์๊ธฐ๋ฅผ ์ฌ์ฉํ๋ฉฐ, ์ ์ฑ ๋ถ์์ ์ํด ์
๋ ฅ ๊ตฌ์ฑ์ด ๊ฒฐ์ ๋๋ค. ์ด ์นฉ์ 65 nm CMOS ๊ธฐ์ ๋ก ์ ์๋์์ผ๋ฉฐ 0.151 mm2์ ๋ฉด์ ์ ์ฐจ์งํ๋ค. ์ ์๋ ์ก์ ๊ธฐ ์์คํ
์ PAM-4 ์ ํธ์ ํจ๊ป 48 Gb/s์ ๋ฐ์ดํฐ ์๋์์ 3.03 pJ/b์ ์๋์ง ํจ์จ์ ๋ณด์ฌ์ค๋ค.
๋ ๋ฒ์งธ ์นฉ์์๋ 3-ํญ FFE ๋ฐ ์ญํ์ T-์ฝ์ผ์ ์ฌ์ฉํ๋ ์ ๋ ฅ ํจ์จ์ ์ธ PAM-4 VCSEL ์ก์ ๊ธฐ๋ฅผ ์ ์ํ๋ค. ์์ ๋ณด๊ฐ๊ธฐ(PI)๋ ๋ถ๋ถ ๊ฐ๊ฒฉ FFE ํญ์ ์์ฑํ๊ณ 4-์์ ํด๋ญ ์ค๋ฅ๋ฅผ ์์ ํ๋ ๋ฐ ์ฌ์ฉ๋๋ค. ์ง๋ ฌํ ์ ๋ ฅ ์๋น๋ฅผ ์ค์ด๊ธฐ ์ํด ์ถ๋ ฅ ๋๋ผ์ด๋ฒ์์ MSB์ LSB๋ฅผ ๋ ๊ฐ์ 4:1 MUX๋ฅผ ํตํด ๊ฒฐํฉํ๋ ๋์ 8:1 MUX๋ฅผ ํตํด PAM-4๋ก ๊ฒฐํฉํ๋ ํ๋ก๊ฐ ์ ์๋๋ค. ๋ด๋ถ ๋ฐ ์ถ๋ ฅ ๋
ธ๋์์ T-์ฝ์ผ์ ๋์ญํญ์ ์ฆ๊ฐ์ํค๊ณ ๊ธฐํธ ๊ฐ ๊ฐ์ญ(ISI)์ ์ ๊ฑฐํ๋ค. ์ถ๋ ฅ ๋คํธ์ํฌ์์ ์ญํ์ T-์ฝ์ผ์ T-์ฝ์ผ์ด ์๋ ๊ฒฝ์ฐ๋ณด๋ค ๋์ญํญ์ 1.61๋ฐฐ ์ฆ๊ฐ์ํจ๋ค. VCSEL ๋๋ผ์ด๋ฒ๋ ์๊ทน ๊ตฌ๋ ๋ฐ ์ ๋ ฅ ๊ฐ์๋ฅผ ์ํด ๋์ VSS ๋๋ฉ์ธ์ ๋ฐฐ์น๋๋ค. ์ด ์นฉ์ 40 nm CMOS ๊ธฐ์ ๋ก ์ ์๋์๋ค. ์ ์๋ VCSEL ์ก์ ๊ธฐ๋ ๊ฐ๊ฐ 3.03pJ/b์ 2.09pJ/b์ ์ ๋ ฅ ํจ์จ๋ก ์ต๋ 48Gb/s NRZ์ 64Gb/s PAM-4๊น์ง ์๋ํ๋ค.ABSTRACT I
CONTENTS III
LIST OF FIGURES V
LIST OF TABLES IX
CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 5
CHAPTER 2 BACKGROUND OF HIGH-SPEED INTERFACE 6
2.1 OVERVIEW 6
2.2 BASIS OF DATA CENTER ARCHITECTURE 9
2.3 SHORT-REACH INTERFACE STANDARDS 12
2.4 ANALYSES OF BANDWIDTH EXTENSION TECHNIQUES 16
2.4.1 FRACTIONALLY-SPACED FFE 16
2.4.2 TRANSMISSION LINE 21
2.4.3 INDUCTOR 24
2.4.4 T-COIL 33
CHAPTER 3 DESIGN OF 48 GB/S PAM-4 ELECTRICAL TRANSMITTER IN 65 NM CMOS 43
3.1 OVERVIEW 43
3.2 FFE BASED ON DOUBLE-SHIELDED COPLANAR WAVEGUIDE 46
3.2.1 BASIC CONCEPT 46
3.2.2 PROPOSED DOUBLE-SHIELDED COPLANAR WAVEGUIDE 47
3.3 DESIGN CONSIDERATION ON 4:1 MUX 50
3.4 PROPOSED PAM-4 ELECTRICAL TRANSMITTER 53
3.5 MEASUREMENT 57
CHAPTER 4 DESIGN OF 64 GB/S PAM-4 OPTICAL TRANSMITTER IN 40 NM CMOS 64
4.1 OVERVIEW 64
4.2 DESIGN CONSIDERATION OF OPTICAL TRANSMITTER 66
4.3 PROPOSED PAM-4 VCSEL TRANSMITTER 69
4.4 MEASUREMENT 82
CHAPTER 5 CONCLUSIONS 88
BIBLIOGRAPHY 90
์ด ๋ก 101๋ฐ
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS
This paper presents a 40-Gb/s transmitter (TX) and receiver (RX) chipset for chip-to-chip communications in a 65-nm CMOS process. The TX implements a quarter-rate multi-multiplexer (MUX)-based four-tap feed-forward equalizer (FFE), where a charge-sharing-effect elimination technique is introduced into the 4:1 MUX to optimize its jitter performance and power efficiency. The RX employs a two-stage continuous-time linear equalizer as the analog front end and integrates a low-cost sign-based zero-forcing engine relying on edge-data correlation to automatically adjust the tap weights of the TX-FFE. By embedding low-pass filters with an adaptively adjusting bandwidth into the data-sampling path and adopting high-linearity compensating phase interpolators, the clock data recovery achieves both high jitter tolerance and low jitter generation. The fabricated TX and RX chipset delivers 40-Gb/s PRBS data at BER 16-dB loss at half-baud frequency, while consuming a total power of 370 mW
์ต์ ์ ๊ฐ๊น์ด ํ์ด๋ฐ ์ ์์ ์ํด ์น์ฐ์น ๋ฐ์ดํฐ ๋ ๋ฒจ๊ณผ ๋ ๊ฒฝ์ฌ ๋ํ ํฐ๋ฅผ ์ฌ์ฉํ ์ต๋ ๋ํฌ๊ธฐ์ถ์ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก ์ค๊ณ
ํ์๋
ผ๋ฌธ (๋ฐ์ฌ) -- ์์ธ๋ํ๊ต ๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2021. 2. ์ ๋๊ท .์ด ๋
ผ๋ฌธ์์๋ ์ต์-๋นํธ ๋นํธ ์๋ฌ์จ (BER)์ ๋ํ ์ต๋ ๋ํฌ๊ธฐ ์ถ์
CDR (MET-CDR)์ ์ค๊ณ๊ฐ ์ ์๋์๋ค. ์ ์ ๋ CDR ์ ์ต์ ์ ์ํ๋ง
๋จ๊ณ๋ฅผ ์ฐพ๊ธฐ ์ํด ๋ฐ๋ณต ์ ์ฐจ๋ฅผ ๊ฐ์ง BER ์นด์ดํฐ ๋๋ ์์ด ๋ชจ๋ํฐ๊ฐ ํ
์ํ์ง ์๋ค. ์๋ฌ ์ํ๋ฌ ์ถ๋ ฅ์ ๊ฐ์ค์น๋ฅผ ๋์ด ๋ํ์ฌ ์ป์ ์น์ฐ์น ๋ฐ
์ดํฐ ๋ ๋ฒจ (biased dLev) ์ ์ฌ์ ์ปค์ ISI(pre-cursor ISI) ์ ์ ๋ณด๋ ๊ณ ๋ คํ
๋ ๋์ด ์ ๋ณด๋ฅผ ์ถ์ถํ๋ค. ๋ธํ T ๋งํผ์ ์๊ฐ ์ฐจ์ด๋ฅผ ๋ ์ง์ ์์ ์๋
ํ๋ ๋ ์ํ๋ฌ๋ ํ์ฌ ๋ ๋์ด์ ๋ ๊ธฐ์ธ๊ธฐ์ ๊ทน์ฑ์ ๊ฐ์งํ๊ณ , ์ด ์ ๋ณด
๋ฅผ ํตํด ์ ์ํ๋ CDR ์ ๋ ๊ธฐ์ธ๊ธฐ๊ฐ 0 ์ด๋๋ ์ต๋ ๋ ๋์ด๋ก ์๋ ดํ
๋ค. ์ธก์ ๊ฒฐ๊ณผ๋ ์ต๋ ๋ ๋์ด์ ์ต์ BER ์ ์ํ๋ง ์์น๊ฐ ์ ์ผ์น ํจ
์ ๋ณด์ฌ์ค๋ค. 28nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋ ์์ ๊ธฐ ์นฉ์ 23.5dB ์ ์ฑ๋
์์ค์ด ์๋ ์ํ์์ 26Gb/s ์์ ๋์ ๊ฐ๋ฅํ๋ค. 0.25UI ์ ์์ด ์คํ๋
์ ๊ฐ์ง๋ฉฐ, 87mW ์ ํ์๋ฅผ ์๋นํ๋ค.In this thesis, design of a maximum-eye-tracking CDR (MET-CDR) for minimum bit error rate (BER) is proposed. The proposed CDR does not require a BER coun-ter or an eye-opening monitor with any iterative procedure to find the near-optimal sampling phase. The biased data-level obtained from the weighted sum of error sampler outputs, UP and DN, extracts the actual eye height information in the presence of pre-cursor ISI. Two samplers operating on two slightly different tim-ings detect the current eye height and the polarity of the eye slope so that the CDR tracks the maximum eye height where the slope becomes zero. Measured results show that the sampling phase of the maximum eye height and that of the mini-mum BER match well. A prototype receiver fabricated in 28 nm CMOS process operates at 26 Gb/s with an eye-opening of 0.25 UI and consumes 87 mW while equalizing 23.5 dB of loss at 13 GHz.ABSTRACT I
CONTENTS II
LIST OF FIGURES IV
LIST OF TABLES VIII
CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 4
CHAPTER 2 BACKGROUNDS 5
2.1 RECEIVER FRONT-END 5
2.1.1 CHANNEL 7
2.1.2 EQUALIZER 17
2.1.3 CDR 32
2.2 PRIOR ARTS ON CLOCK RECOVERY 39
2.2.1 BB-CDR 39
2.2.2 BER-BASED CDR 41
2.2.3 EOM-BASED CDR 44
2.3 CONCEPT OF THE PROPOSED CDR 47
CHAPTER 3 MAXIMUM-EYE-TRACKING CDR WITH BIASED DATA-LEVEL AND EYE SLOPE DETECTOR 49
3.1 OVERVIEW 49
3.2 DESIGN OF MET-CDR 50
3.2.1 EYE HEIGHT INFORMATION FROM BIASED DATA-LEVEL 50
3.2.2 EYE SLOPE DETECTOR AND ADAPTATION ALGORITHM 60
3.2.3 ARCHITECTURE AND IMPLEMENTATION 67
3.2.4 VERIFICATION OF THE ALGORITHM 71
3.2.5 ANALYSIS ON THE BIASED DATA-LEVEL 76
3.3 EXPANSION OF MET-CDR TO PAM4 SIGNALING 84
3.3.1 MET-CDR WITH PAM4 84
3.3.2 CONSIDERATIONS FOR PAM4 87
CHAPTER 4 MEASUREMENT RESULTS 89
CHAPTER 5 CONCLUSION 99
APPENDIX A MATLAB CODE FOR SIMULATING RECEIVER WITH MET-CDR 100
BIBLIOGRAPHY 105
์ด ๋ก 113Docto
์ ์ ๋ ฅ, ์ ๋ฉด์ ์ ์ ์ก์์ ๊ธฐ ์ค๊ณ๋ฅผ ์ํ ํ๋ก ๊ธฐ์
ํ์๋
ผ๋ฌธ (๋ฐ์ฌ)-- ์์ธ๋ํ๊ต ๋ํ์ : ์ ๊ธฐยท์ปดํจํฐ๊ณตํ๋ถ, 2016. 8. ์ ๋๊ท .In this thesis, novel circuit techniques for low-power and area-efficient wireline transceiver, including a phase-locked loop (PLL) based on a two-stage ring oscillator, a scalable voltage-mode transmitter, and a forwarded-clock (FC) receiver based on a delay-locked-loop (DLL) based per-pin deskew, are proposed.
At first, a two-stage ring PLL that provides a four-phase, high-speed clock for a quarter-rate TX in order to minimize power consumption is presented. Several analyses and verification techniques, ranging from the clocking architectures for a high-speed TX to oscillation failures in a two-stage ring oscillator, are addressed in this thesis. A tri-state-inverterโbased frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed PLL fabricated in the 65-nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply at 10 GHz. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB.
Secondly, a voltage-mode (VM) transmitter which offers a wide operation range of 6 to 32 Gb/s, controllable pre-emphasis equalization and output voltage swing without altering output impedance, and a power supply scalability is presented. A quarter-rate clocking architecture is employed in order to maximize the scalability and energy efficiency across the variety of operating conditions. A P-over-N VM driver is used for CMOS compatibility and wide voltage-swing range required for various I/O standards. Two supply regulators calibrate the output impedance of the VM driver across the wide swing and pre-emphasis range. A single phase-locked loop is used to provide a wide frequency range of 1.5-to-8 GHz. The prototype chip is fabricated in 65-nm CMOS technology and occupies active area of 0.48x0.36 mm2. The proposed transmitter achieves 250-to-600-mV single-ended swing and exhibits the energy efficiency of 2.10-to-2.93 pJ/bit across the data rate of 6-to-32 Gb/s.
And last, this thesis describes a power and area-efficient FC receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a DLL-based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-UIpp sinusoidal jitter of 300 MHz.Chapter 1. Introduction 1
1.1. Motivation 1
1.2. Thesis organization 5
Chapter 2. Phase-Locked Loop Based on Two-Stage Ring Oscillator 7
2.1. Overivew 7
2.2. Background and Analysis of a Two-stage Ring Oscillator 11
2.3. Circuit Implementation of The Proposed PLL 25
2.4. Measurement Results 33
Chapter 3. A Scalable Voltage-Mode Transmitter 37
3.1. Overview 37
3.2. Design Considerations on a Scalable Serial Link Transmitter 40
3.3. Circuit Implementation 46
3.4. Measurement Results 56
Chapter 4. Delay-Locked Loop Based Forwarded-Clock Receiver 62
4.1. Overview 62
4.2. Timing and Data Recovery in a Serial Link 65
4.3. DLL-Based Forwarded-Clock Receiver Characteristics 70
4.4. Circuit Implementation 79
4.5. Measurement Results 89
Chapter 5. Conclusion 94
Appendix 96
Appendix A. Design flow to optimize a high-speed ring oscillator 96
Appendix B. Reflection Issues in N-over-N Voltage-Mode Driver 99
Appendix C. Analysis on output swing and power consumption of the P-over-N voltage-mode driver 107
Appendix D. Loop Dynamics of DLL 112
Bibliography 121
Abstract 128Docto
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