136 research outputs found
MeLPUF: Memory in Logic PUF
Physical Unclonable Functions (PUFs) are used for securing electronic designs
across the implementation spectrum ranging from lightweight FPGA to
server-class ASIC designs. However, current PUF implementations are vulnerable
to model-building attacks; they often incur significant design overheads and
are challenging to configure based on application-specific requirements. These
factors limit their application, primarily in the case of the system on chip
(SoC) designs used in diverse applications. In this work, we propose MeL-PUF -
Memory-in-Logic PUF, a low-overhead, distributed, and synthesizable PUF that
takes advantage of existing logic gates in a design and transforms them to
create cross-coupled inverters (i.e. memory cells) controlled by a PUF control
signal. The power-up states of these memory cells are used as the source of
entropy in the proposed PUF architecture. These on-demand memory cells can be
distributed across the combinational logic of various intellectual property
(IP) blocks in a system on chip (SoC) design. They can also be synthesized with
a standard logic synthesis tool to meet the area,power, or performance
constraints of a design. By aggregating the power-up states from multiple such
memory cells, we can create a PUF signature or digital fingerprint of varying
size. We evaluate the MeL-PUF signature quality with both circuit-level
simulations as well as with measurements in FPGA devices. We show that MeL-PUF
provides high-quality signatures in terms of uniqueness, randomness, and
robustness, without incurring large overheads. We also suggest additional
optimizations that can be leveraged to improve the performance of MeL-PUF.Comment: 5 pages, 16 figure
Hybrid PUF Design using Bistable Ring PUF and Chaotic Network
Physical Unclonable Function(PUF) is lightweight hardware that provides affordable security for electronic devices and systems which can eliminate the use of the conventional cryptographic system which uses large area and storage. Among the several models, Bi-stable Ring PUF(BR-PUF) is considered as a secure and efficient PUF model since it has no mathematical model still found. In this thesis, we proposed a modified design called a hybrid model of BR-PUF and a Chaotic network to improve the BR-PUF resilience against machine learning attacks. We experimented with the current modification XOR technique to analyze the uniqueness, reliability and resource consumption. The proposed PUF was implemented on Xilinx Artix 7 FPGA and the PUF metrics were captured and compared with the results of XOR-ed based PUF integration techniques. The lightweight PUF model was achieved with 16% resource reduction when compared to XOR-ed BR PUF with no compromise in PUF quality
A Physical Unclonable Function Based on Inter-Metal Layer Resistance Variations and an Evaluation of its Temperature and Voltage Stability
Keying material for encryption is stored as digital bistrings in non-volatile memory (NVM) on FPGAs and ASICs in current technologies. However, secrets stored this way are not secure against a determined adversary, who can use probing attacks to steal the secret. Physical Unclonable functions (PUFs) have emerged as an alternative. PUFs leverage random manufacturing variations as the source of entropy for generating random bitstrings, and incorporate an on-chip infrastructure for measuring and digitizing the corresponding variations in key electrical parameters, such as delay or voltage. PUFs are designed to reproduce a bitstring on demand and therefore eliminate the need for on-chip storage. In this dissertation, I propose a kind of PUF that measures resistance variations in inter-metal layers that define the power grid of the chip and evaluate its temperature and voltage stability. First, I introduce two implementations of a power grid-based PUF (PG-PUF). Then, I analyze the quality of bit strings generated without considering environmental variations from the PG-PUFs that leverage resistance variations in: 1) the power grid metal wires in 60 copies of a 90 nm chip and 2) in the power grid metal wires of 58 copies of a 65 nm chip. Next, I carry out a series of experiments in a set of 63 chips in IBM\u27s 90 nm technology at 9 TV corners, i.e., over all combination of 3 temperatures: -40oC, 25oC and 85oC and 3 voltages: nominal and +/-10% of the nominal supply voltage. The randomness, uniqueness and stability characteristics of bitstrings generated from PG-PUFs are evaluated. The stability of the PG-PUF and an on-chip voltage-to-digital (VDC) are also evaluated at 9 temperature-voltage corners. I introduce several techniques that have not been previously described, including a mechanism to eliminate voltage trends or \u27bias\u27 in the power grid voltage measurements, as well as a voltage threshold, Triple-Module-Redundancy (TMR) and majority voting scheme to identify and exclude unstable bits
Printed Electronics-Based Physically Unclonable Functions for Lightweight Security in the Internet of Things
Die moderne Gesellschaft strebt mehr denn je nach digitaler KonnektivitĂ€t - ĂŒberall und zu jeder Zeit - was zu Megatrends wie dem Internet der Dinge (Internet of Things, IoT) fĂŒhrt. Bereits heute kommunizieren und interagieren âDingeâ autonom miteinander und werden in Netzwerken verwaltet. In Zukunft werden Menschen, Daten und Dinge miteinander verbunden sein, was auch als Internet von Allem (Internet of Everything, IoE) bezeichnet wird. Milliarden von GerĂ€ten werden in unserer tĂ€glichen Umgebung allgegenwĂ€rtig sein und ĂŒber das Internet in Verbindung stehen.
Als aufstrebende Technologie ist die gedruckte Elektronik (Printed Electronics, PE) ein SchlĂŒsselelement fĂŒr das IoE, indem sie neuartige GerĂ€tetypen mit freien Formfaktoren, neuen Materialien auf einer Vielzahl von Substraten mit sich bringt, die flexibel, transparent und biologisch abbaubar sein können. DarĂŒber hinaus ermöglicht PE neue Freiheitsgrade bei der Anpassbarkeit von Schaltkreisen sowie die kostengĂŒnstige und groĂflĂ€chige Herstellung am Einsatzort.
Diese einzigartigen Eigenschaften von PE ergÀnzen herkömmliche Technologien auf Siliziumbasis. Additive Fertigungsprozesse ermöglichen die Realisierung von vielen zukunftstrÀchtigen Anwendungen wie intelligente Objekte, flexible Displays, Wearables im Gesundheitswesen, umweltfreundliche Elektronik, um einige zu nennen.
Aus der Sicht des IoE ist die Integration und Verbindung von Milliarden heterogener GerĂ€te und Systeme eine der gröĂten zu lösenden Herausforderungen. Komplexe HochleistungsgerĂ€te interagieren mit hochspezialisierten, leichtgewichtigen elektronischen GerĂ€ten, wie z.B. Smartphones mit intelligenten Sensoren. Daten werden in der Regel kontinuierlich gemessen, gespeichert und mit benachbarten GerĂ€ten oder in der Cloud ausgetauscht. Dabei wirft die FĂŒlle an gesammelten und verarbeiteten Daten Bedenken hinsichtlich des Datenschutzes und der Sicherheit auf.
Herkömmliche kryptografische Operationen basieren typischerweise auf deterministischen Algorithmen, die eine hohe Schaltungs- und SystemkomplexitĂ€t erfordern, was sie wiederum fĂŒr viele leichtgewichtige GerĂ€te ungeeignet macht.
Es existieren viele Anwendungsbereiche, in denen keine komplexen kryptografischen Operationen erforderlich sind, wie z.B. bei der GerĂ€teidentifikation und -authentifizierung. Dabei hĂ€ngt das Sicherheitslevel hauptsĂ€chlich von der QualitĂ€t der Entropiequelle und der VertrauenswĂŒrdigkeit der abgeleiteten SchlĂŒssel ab. Statistische Eigenschaften wie die Einzigartigkeit (Uniqueness) der SchlĂŒssel sind von groĂer Bedeutung, um einzelne EntitĂ€ten genau unterscheiden zu können.
In den letzten Jahrzehnten hat die Hardware-intrinsische Sicherheit, insbesondere Physically Unclonable Functions (PUFs), eine groĂe Strahlkraft hinsichtlich der Bereitstellung von Sicherheitsfunktionen fĂŒr IoT-GerĂ€te erlangt. PUFs verwenden ihre inhĂ€renten Variationen, um gerĂ€tespezifische eindeutige Kennungen abzuleiten, die mit FingerabdrĂŒcken in der Biometrie vergleichbar sind.
Zu den gröĂten Potenzialen dieser Technologie gehören die Verwendung einer echten Zufallsquelle, die Ableitung von SicherheitsschlĂŒsseln nach Bedarf sowie die inhĂ€rente SchlĂŒsselspeicherung.
In Kombination mit den einzigartigen Merkmalen der PE-Technologie werden neue Möglichkeiten eröffnet, um leichtgewichtige elektronische GerĂ€te und Systeme abzusichern. Obwohl PE noch weit davon entfernt ist, so ausgereift und zuverlĂ€ssig wie die Siliziumtechnologie zu sein, wird in dieser Arbeit gezeigt, dass PE-basierte PUFs vielversprechende Sicherheitsprimitiven fĂŒr die SchlĂŒsselgenerierung zur eindeutigen GerĂ€teidentifikation im IoE sind.
Dabei befasst sich diese Arbeit in erster Linie mit der Entwicklung, Untersuchung und Bewertung von PE-basierten PUFs, um Sicherheitsfunktionen fĂŒr ressourcenbeschrĂ€nkte gedruckte GerĂ€te und Systeme bereitzustellen.
Im ersten Beitrag dieser Arbeit stellen wir das skalierbare, auf gedruckter Elektronik basierende Differential Circuit PUF (DiffC-PUF) Design vor, um sichere SchlĂŒssel fĂŒr Sicherheitsanwendungen fĂŒr ressourcenbeschrĂ€nkte GerĂ€te bereitzustellen. Die DiffC-PUF ist als hybride Systemarchitektur konzipiert, die siliziumbasierte und gedruckte Komponenten enthĂ€lt. Es wird eine eingebettete PUF-Plattform entwickelt, um die Charakterisierung von siliziumbasierten und gedruckten PUF-Cores in groĂem MaĂstab zu ermöglichen.
Im zweiten Beitrag dieser Arbeit werden siliziumbasierte PUF-Cores auf Basis diskreter Komponenten hergestellt und statistische Tests unter realistischen Betriebsbedingungen durchgefĂŒhrt. Eine umfassende experimentelle Analyse der PUF-Sicherheitsmetriken wird vorgestellt. Die Ergebnisse zeigen, dass die DiffC-PUF auf Siliziumbasis nahezu ideale Werte fĂŒr die Uniqueness- und Reliability-Metriken aufweist. DarĂŒber hinaus werden die IdentifikationsfĂ€higkeiten der DiffC-PUF untersucht, und es stellte sich heraus, dass zusĂ€tzliches Post-Processing die Identifizierbarkeit des Identifikationssystems weiter verbessern kann.
Im dritten Beitrag dieser Arbeit wird zunÀchst ein Evaluierungsworkflow zur Simulation von DiffC-PUFs basierend auf gedruckter Elektronik vorgestellt, welche auch als Hybrid-PUFs bezeichnet werden. Hierbei wird eine Python-basierte Simulationsumgebung vorgestellt, welche es ermöglicht, die Eigenschaften und Variationen gedruckter PUF-Cores basierend auf Monte Carlo (MC) Simulationen zu untersuchen. Die Simulationsergebnisse zeigen, dass die Sicherheitsmetriken im besten Betriebspunkt nahezu ideal sind.
Des Weiteren werden angefertigte PE-basierte PUF-Cores fĂŒr statistische Tests unter verschiedenen Betriebsbedingungen, einschlieĂlich Schwankungen der Umgebungstemperatur, der relativen Luftfeuchtigkeit und der Versorgungsspannung betrieben. Die experimentell bestimmten Resultate der Uniqueness-, Bit-Aliasing- und Uniformity-Metriken stimmen gut mit den Simulationsergebnissen ĂŒberein. Der experimentell ermittelte durchschnittliche Reliability-Wert ist relativ niedrig, was durch die fehlende Passivierung und Einkapselung der gedruckten Transistoren erklĂ€rt werden kann. Die Untersuchung der IdentifikationsfĂ€higkeiten basierend auf den PUF-Responses zeigt, dass die Hybrid-PUF ohne zusĂ€tzliches Post-Processing nicht fĂŒr kryptografische Anwendungen geeignet ist. Die Ergebnisse zeigen aber auch, dass sich die Hybrid-PUF zur GerĂ€teidentifikation eignet.
Der letzte Beitrag besteht darin, in die Perspektive eines Angreifers zu wechseln. Um die SicherheitsfĂ€higkeiten der Hybrid-PUF beurteilen zu können, wird eine umfassende Sicherheitsanalyse nach Art einer Kryptoanalyse durchgefĂŒhrt. Die Analyse der Entropie der Hybrid-PUF zeigt, dass seine AnfĂ€lligkeit fĂŒr Angriffe auf Modellbasis hauptsĂ€chlich von der eingesetzten Methode zur Generierung der PUF-Challenges abhĂ€ngt. DarĂŒber hinaus wird ein Angriffsmodell eingefĂŒhrt, um die Leistung verschiedener mathematischer Klonangriffe auf der Grundlage von abgehörten Challenge-Response Pairs (CRPs) zu bewerten. Um die Hybrid-PUF zu klonen, wird ein Sortieralgorithmus eingefĂŒhrt und mit hĂ€ufig verwendeten Classifiers fĂŒr ĂŒberwachtes maschinelles Lernen (ML) verglichen, einschlieĂlich logistischer Regression (LR), Random Forest (RF) sowie Multi-Layer Perceptron (MLP).
Die Ergebnisse zeigen, dass die Hybrid-PUF anfĂ€llig fĂŒr modellbasierte Angriffe ist. Der Sortieralgorithmus profitiert von kĂŒrzeren Trainingszeiten im Vergleich zu den ML-Algorithmen. Im Falle von fehlerhaft abgehörten CRPs ĂŒbertreffen die ML-Algorithmen den Sortieralgorithmus
Design, Fabrication, and Run-time Strategies for Hardware-Assisted Security
Today, electronic computing devices are critically involved in our daily lives, basic infrastructure, and national defense systems. With the growing number of threats against them, hardware-based security features offer the best chance for building secure and trustworthy cyber systems. In this dissertation, we investigate ways of making hardware-based security into a reality with primary focus on two areas: Hardware Trojan Detection and Physically Unclonable Functions (PUFs). Hardware Trojans are malicious modifications made to original IC designs or layouts that can jeopardize the integrity of hardware and software platforms. Since most modern systems critically depend on ICs, detection of hardware Trojans has garnered significant interest in academia, industry, as well as governmental agencies. The majority of existing detection schemes focus on test-time because of the limited hardware resources available at run-time. In this dissertation, we explore innovative run-time solutions that utilize on-chip thermal sensor measurements and fundamental estimation/detection theory to expose changes in IC power/thermal profile caused by Trojan activation. The proposed solutions are low overhead and also generalizable to many other sensing modalities and problem instances. Simulation results using state-of-the-art tools on publicly available Trojan benchmarks verify that our approaches can detect Trojans quickly and with few false positives. Physically Unclonable Functions (PUFs) are circuits that rely on IC fabrication variations to generate unique signatures for various security applications such as IC authentication, anti-counterfeiting, cryptographic key generation, and tamper resistance. While the existence of variations has been well exploited in PUF design, knowledge of exactly how variations come into existence has largely been ignored. Yet, for several decades the Design-for-Manufacturability (DFM) community has actually investigated the fundamental sources of these variations. Furthermore, since manufacturing variations are often harmful to IC yield, the existing DFM tools have been geared towards suppressing them (counter-intuitive for PUFs). In this dissertation, we make several improvements over current state-of-the-art work in PUFs. First, our approaches exploit existing DFM models to improve PUFs at physical layout and mask generation levels. Second, our proposed algorithms reverse the role of standard DFM tools and extend them towards improving PUF quality without harming non-PUF portions of the IC. Finally, since our approaches occur after design and before fabrication, they are applicable to all types of PUFs and have little overhead in terms of area, power, etc. The innovative and unconventional techniques presented in this dissertation should act as important building blocks for future work in cyber security
Recommended from our members
On Improving Robustness of Hardware Security Primitives and Resistance to Reverse Engineering Attacks
The continued growth of information technology (IT) industry and proliferation of interconnected devices has aggravated the problem of ensuring security and necessitated the need for novel, robust solutions. Physically unclonable functions (PUFs) have emerged as promising secure hardware primitives that can utilize the disorder introduced during manufacturing process to generate unique keys. They can be utilized as \textit{lightweight} roots-of-trust for use in authentication and key generation systems. Unlike insecure non-volatile memory (NVM) based key storage systems, PUFs provide an advantage -- no party, including the manufacturer, should be able to replicate the physical disorder and thus, effectively clone the PUF. However, certain practical problems impeded the widespread deployment of PUFs. This dissertation addresses such problems of (i) reliability and (ii) unclonability. Also, obfuscation techniques have proven necessary to protect intellectual property in the presence of an untrusted supply chain and are needed to aid against counterfeiting. This dissertation explores techniques utilizing layout and logic-aware obfuscation. Collectively, we present secure and cost-effective solutions to address crucial hardware security problems
Recommended from our members
Threat Analysis, Countermeaures and Design Strategies for Secure Computation in Nanometer CMOS Regime
Advancements in CMOS technologies have led to an era of Internet Of Things (IOT), where the devices have the ability to communicate with each other apart from their computational power. As more and more sensitive data is processed by embedded devices, the trend towards lightweight and efficient cryptographic primitives has gained significant momentum. Achieving a perfect security in silicon is extremely difficult, as the traditional cryptographic implementations are vulnerable to various active and passive attacks. There is also a threat in the form of hardware Trojans inserted into the supply chain by the untrusted third-party manufacturers for economic incentives. Apart from the threats in various forms, some of the embedded security applications such as random number generators (RNGs) suffer from the impacts of process variations and noise in nanometer CMOS. Despite their disadvantages, the random and unique nature of process variations can be exploited for generating unique identifiers and can be of tremendous use in embedded security.
In this dissertation, we explore techniques for precise fault-injection in cryptographic hardware based on voltage/temperature manipulation and hardware Trojan insertion. We demonstrate the effectiveness of these techniques by mounting fault attacks on state-of-the-art ciphers. Physically Unclonable Functions (PUFs) are novel cryptographic primitives for extracting secret keys from complex manufacturing variations in integrated circuits (ICs). We explore the vulnerabilities of some of the popular strong PUF architectures to modeling attacks using Machine Learning (ML) algorithms. The attacks use silicon data from a test chip manufactured in IBM 32nm silicon-on-insulator (SOI) technology. Attack results demonstrate that the majority of strong PUF architectures can be predicted to very high accuracies using limited training data. We also explore the techniques to exploit unreliable data from strong PUF architectures and effectively use them to improve the prediction accuracies of modeling attacks. Motivated by the vulnerabilities of existing PUF architectures, we present a novel modeling attack resistant PUF architecture based on non-linear computing elements. Post-silicon validation results are used to demonstrate the effectiveness of the non-linear PUF architecture against modeling and fault-injection attacks. Apart from the techniques to improve the security of PUF circuits, we also present novel solutions to improve the performance of PUF circuits from the perspectives of IC fabrication and system/protocol design. Finally, we present a statistical benchmark suite to evaluate PUFs in conceptualization phase and also to enable fine-grained security assessments for varying PUF parameters. Data compressibility analyses for validating the statistical benchmark suite are also presented
ç©çè€èŁœäžèœéąæ°ă«ăăăćźć šæ§ăźè©äŸĄăšćäžă«éąăăç 究
In this thesis, we focus on Physically Unclonable Functions (PUFs), which are expected as one of the most promising cryptographic primitives for secure chip authentication. Generally, PUFbased authentication is achieved by two approaches: (A) using a PUF itself, which has multiple challenge (input) and response (output) pairs, or (B) using a cryptographic function, the secret key of which is generated from a PUF with a single challenge-response pair (CRP). We contribute to:(1) evaluate the security of Approach (A), and (2) improve the security of Approach (B). (1) Arbiter-based PUFs were the most feasible type of PUFs, which was used to construct Approach (A). However, Arbiter-based PUFs have a vulnerability; if an attacker knows some CRPs, she/he can predict the remaining unknown CRPs with high probability. Bistable Ring PUF (BR-PUF) was proposed as an alternative, but has not been evaluated by third parties. In this thesis, in order to construct Approach (A) securely, we evaluate the difficulty of predicting responses of a BR-PUF experimentally. As a result, the same responses are frequently generated for two challenges with small Hamming distance. Also, particular bits of challenges have a great impact on the responses. In conclusion, BR-PUFs are not suitable for achieving Approach (A)securely. In future work, we should discuss an alternative PUF suitable for secure Approach (A).(2) In order to achieve Approach (B) securely, a secret key ? generated from a PUF response?should have high entropy. We propose a novel method of extracting high entropy from PUF responses. The core idea is to effectively utilize the information on the proportion of â1âs including in repeatedly-measured PUF responses. We evaluate its effectiveness by fabricated test chips. As a result, the extracted entropy is about 1.72 times as large as that without the proposed method.Finally, we organize newly gained knowledge in this thesis, and discuss a new application of PUF-based technologies.é»æ°é俥性ćŠ201
- âŠ