Alternative gate dielectrics and application in nanocrystal memory

Ph.DDOCTOR OF PHILOSOPH

Commercialization of germanium based nanocrystal memory

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references.This thesis explores the commercialization of germanium-based nanocrystal memories. Demand for smaller and faster electronics and embedded systems supports the development of high-density, low-power non-volatile electronic memory devices. Flash memory cells designed for ten years of data retention require the use of a thick tunneling oxide. This compromises writing and reading speed as well as endurance. A smaller device size can be achieved and speed and can be improved by decreasing the oxide thickness. However, significant charge leakage will occur if the oxide is too thin, which will reduce the data retention time dramatically. This imposes a limit to the amount by which the oxide thickness can be decreased in conventional devices. Research has shown that by incorporating nanocrystals in the tunnel oxide, charge traps are created which reduce charge leakage and improve endurance through charge-storage redundancy. By replacing the conventional floating gate memory with one using Si or Ge nanocrystals, the nonvolatile memory exhibits high programming speed with low programming voltage and superior retention time, and yet is compatible with conventional silicon technology. This thesis provides an analysis of competing technologies, an intellectual property analysis, costs modeling as well as ways to improve nanocrystal memories in order to compete with other forms of emerging technologies to replace conventional Flash memories.by Kian Chiew Seow.M.Eng

Scalable and high-sensitivity readout of silicon quantum devices

Quantum computing is predicted to provide unprecedented enhancements in computational power. A quantum computer requires implementation of a well-defined and controlled quantum system of many interconnected qubits, each defined using fragile quantum states. The interest in a spin-based quantum computer in silicon stems from demonstrations of very long spin-coherence times, high-fidelity single spin control and compatibility with industrial mass-fabrication. Industrial scale fabrication of the silicon platform offers a clear route towards a large-scale quantum computer, however, some of the processes and techniques employed in qubit demonstrators are incompatible with a dense and foundry-fabricated architecture. In particular, spin-readout utilises external sensors that require nearly the same footprint as qubit devices. In this thesis, improved readout techniques for silicon quantum devices are presented and routes towards implementation of a scalable and high-sensitivity readout architecture are investigated. Firstly, readout sensitivity of compact gate-based sensors is improved using a high-quality factor resonator and Josephson parametric amplifier that are fabricated separately from quantum dots. Secondly, an integrated transistor-based control circuit is presented using which sequential readout of two quantum dot devices using the same gate-based sensor is achieved. Finally, a large-scale readout architecture based on random-access and frequency multiplexing is introduced. The impact of readout circuit footprint on readout sensitivity is determined, showing routes towards integration of conventional circuits with quantum devices in a dense architecture, and a fault-tolerant architecture based on mediated exchange is introduced, capable of relaxing the limitations on available control circuit footprint per qubit. Demonstrations are based on foundry-fabricated transistors and few-electron quantum dots, showing that industry fabrication is a viable route towards quantum computation at a scale large enough to begin addressing the most challenging computational problems

Nanocrystals for nanodot memories : ion beam synthesis and electrical studies

[no abstract

Nanodot-based organic memory devices

In this study, resistor-type, diode-type, and transistor-type organic memory devices were investigated, aiming at the low-cost plastic integrated circuit applications. A series of solution-processing techniques including spin-coating, inkjet printing, and self-assembly were employed to fabricate these devices. The organic resistive memory device is based on a novel molecular complex film composed of tetracyanoquinodimethane (TCNQ) and a soluble methanofullerene derivative [6,6]-phenyl C61-butyric acid methyl ester (PCBM). It has an Al/molecules/Al sandwich structure. The molecular layer was formed by spin-coating technique instead of expensive vacuum deposition method. The current-voltage characteristics show that the device switches from the initial \u27low\u27 conduction state to \u27high\u27 conduction state upon application of external electric field at room temperature and return to \u27low\u27 conduction state when a high current pulse is applied. The on/off ratio is over 106. Each state has been found to remain stable for more than five months, even after the external electric field is removed. The PCBM nanodots wrapped by TCNQ molecules can form potential wells for charge trapping, and are believed to be responsible for the memory effects. A rewritable diode memory device was achieved in an improved configuration, i.e., ITO-PEDOT:PSS-PCBM/TCNQ-Al, where a semiconductor polymer PEDOT:PSS is used to form p+-N heterojunction with PCBM/TCNQ. It exhibits a diode characteristic (low conductive) before switching to a high-conductive Poole-Frenkel regime upon applying a positive external bias to ITO. The on/off ratio at +1.0 V is up to 105. Simulation results from Taurus-Medici are in qualitative agreement with the experimental results and the proposed charge storage model. The transistor-type memory device is fabricated on a heavily doped n-type silicon (n+-Si) substrate with a 100 nm thick thermally-grown oxide layer. The n+-Si serves as the gate electrode, while the oxide layer functions as the control gate dielectric. Gold nanoparticles as the charge storage units are deposited on the substrate by electrostatic self-assembly method. A self-assembled multilayer of polyelectrolytes, together with a thin spin-coated poly(4-vinyl phenol) layer, covers the gold nanoparticles and separates them from the poly(3-hexyl thiophene) channel. Conducting polymer PEDOT:PSS is inkjet printed to form the source/drain electrodes. The device exhibits significant hysteresis behavior in its Ids-Vgs characteristics. The charge storage in gold nanodots (diameter = 16 nm) was confirmed by comparing with devices having no gold nanoparticles, although the effects of interfacial traps may be also significant. The data retention time of the transistor memory is about 60 seconds, which needs to be further improved. It appears that this is the first demonstration of memory effects in an organic transistor caused by charge storage in metal nanodots in the gate dielectric. Therefore, the approach reported in this work offers a new direction to make low-cost organic transistor memories

Study of organic molecules and nano-particle/polymer composites for flash memory and switch applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 205-218).Organic materials exhibit fascinating optical and electronic properties which motivate their hybridization with traditional silicon-based electronics in order to achieve novel functionalities and address scaling challenges of these devices. The application of organic molecules and nano-particle/polymer composites for flash memory and switch applications is studied in this dissertation. Facilitating data storage on individual small molecules as the approach the limits in miniaturization for ultra-high density and low power consumption media may enable orders of magnitude increase in data storage capabilities. A floating gate consisting of a thin film of molecules would provide the advantage of a uniform set of identical nano-structured charge storage elements with high molecular area densities which can result in a several-fold higher density of charge-storage sites as compared to quantum dot (QD) memory and even SONOS devices. Additionally, the discrete charge storage in such nano-segmented floating gate designs limits the impact of any tunnel oxide defects to the charge stored in the proximity of the defect site. The charge retention properties of molecular films was investigated in this dissertation by injecting charges via a biased conductive atomic force microscopy (AFM) tip into molecules comprising the thin films. The Kelvin force microscopy (KFM) results revealed minimal changes in the spatial extent of the charge trapping over time after initial injection. Fabricated memory capacitors show a device durability over 105 program/erase cycles and hysteresis window of up to 12.8 V, corresponding to stored charge densities as high as 5.4x 1013 cm-2, suggesting the potential use of organic molecules in high storage capacity memory cells. Also, these results demonstrate that charge storage properties of the molecular trapping layer can be engineered by rearranging molecules and their a-orbital overlaps via addition of dopant molecules. Finally, the design, fabrication, testing and evaluation of a MEMS switch that employs viscoelastic organic polymers doped with nano-particles as the active material is presented in this dissertation. The conductivity of the nano-composite changes 10,000-fold as it is mechanically compressed. In this demonstration the compressive squeeze is applied with electric actuation. Since squeezing initiates the switching behavior, the device is referred to as a "squitch". The squitch is essentially a new type of FET that is compatible with large area processing with printing or photolithography, on rigid or flexible substrates and can exhibit large on-to-off conduction ratio.by Sarah Paydavosi.Ph.D

CHARACTERIZATION OF METAL-OXIDE-SEMICONDUCTOR STRUCTURES AT LOW TEMPERATURES USING SELF-ALIGNED AND VERTICALLY COUPLED ALUMINUM AND SILICON SINGLE-ELECTRON TRANSISTORS

I incorporate an Al-AlOx-Al single-electron transistor (SET) as the gate of a narrow (~ 100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET). Near the MOSFET channel conductance threshold, Coulomb blockade oscillations are observed at about 20 millikelvin, revealing the formation of a Si SET at the Si/SiO2 interface. Based on a simple electrostatic model, the two SET islands are demonstrated to be closely aligned, with an inter-island capacitance approximately equal to 1/3 of the total capacitance of the Si transistor island, indicating that the Si transistor is strongly coupled to the Al transistor. This vertically-aligned Al and Si SET system is used to characterize the background charges in a MOS structure at low temperature, which may also be sources of decoherence for Si quantum computation. A single charge defect, probably either a single charge trap at the Si/SiO2 interface or a single donor in the Si substrate, is detected and the properties of the defect are studied in this dissertation

Embedding Logic and Non-volatile Devices in CMOS Digital Circuits for Improving Energy Efficiency

abstract: Static CMOS logic has remained the dominant design style of digital systems for more than four decades due to its robustness and near zero standby current. Static CMOS logic circuits consist of a network of combinational logic cells and clocked sequential elements, such as latches and flip-flops that are used for sequencing computations over time. The majority of the digital design techniques to reduce power, area, and leakage over the past four decades have focused almost entirely on optimizing the combinational logic. This work explores alternate architectures for the flip-flops for improving the overall circuit performance, power and area. It consists of three main sections. First, is the design of a multi-input configurable flip-flop structure with embedded logic. A conventional D-type flip-flop may be viewed as realizing an identity function, in which the output is simply the value of the input sampled at the clock edge. In contrast, the proposed multi-input flip-flop, named PNAND, can be configured to realize one of a family of Boolean functions called threshold functions. In essence, the PNAND is a circuit implementation of the well-known binary perceptron. Unlike other reconfigurable circuits, a PNAND can be configured by simply changing the assignment of signals to its inputs. Using a standard cell library of such gates, a technology mapping algorithm can be applied to transform a given netlist into one with an optimal mixture of conventional logic gates and threshold gates. This approach was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier in 65nm LP technology. Simulation and chip measurements show more than 30% improvement in dynamic power and more than 20% reduction in core area. The functional yield of the PNAND reduces with geometry and voltage scaling. The second part of this research investigates the use of two mechanisms to improve the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM devices for low voltage operation. The third part of this research focused on the design of flip-flops with non-volatile storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated with both conventional D-flipflop and the PNAND circuits to implement non-volatile logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of system locally when a power interruption occurs. However, manufacturing variations in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading to an overly pessimistic design and consequently, higher energy consumption. A detailed analysis of the design trade-offs in the driver circuitry for performing backup and restore, and a novel method to design the energy optimal driver for a given yield is presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented, in which the backup time is determined on a per-chip basis, resulting in minimizing the energy wastage and satisfying the yield constraint. To achieve a yield of 98%, the conventional approach would have to expend nearly 5X more energy than the minimum required, whereas the proposed tunable approach expends only 26% more energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are designed with the same backup and restore circuitry in 65nm technology. The embedded logic in NV-TLFF compensates performance overhead of NVL. This leads to the possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and- accumulate (MAC) unit is designed to demonstrate the performance benefits of the proposed architecture. Based on the results of HSPICE simulations, the MAC circuit with the proposed NV-TLFF cells is shown to consume at least 20% less power and area as compared to the circuit designed with conventional DFFs, without sacrificing any performance.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

신축성 있고 착용 가능한 탄소 나노튜브 기반 전자 기술

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 협동과정 바이오엔지니어링전공, 2020. 8. 김대형.Networks of carbon nanotubes (CNTs) are a promising candidate for use as a basic building block for next-generation soft electronics, owing to their superior mechanical and electrical properties, chemical stability, and low production cost. In particular, the CNTs, which are produced as a mixture of metallic and semiconducting CNTs via chemical vapor deposition, can be sorted according to their electronic types, which makes them useful for specific purposes: semiconducting CNTs can be employed as channel materials in transistor-based applications and metallic CNTs as electrodes. However, the development of CNT-based electronics for soft applications is still at its infant stage, mainly limited by the lack of solid technologies for developing high-performance deformable devices whose electrical performances are comparable to those fabricated using conventional inorganic materials. In this regard, soft CNT electronics with high mechanical stability and electrical performances have been pursued. First, wearable nonvolatile memory modules and logic gates were fabricated by employing networks of semiconducting CNTs as the channel materials, with strain-tolerant device designs for high mechanical stability. The fabricated devices exhibited low operation voltages, high device-to-device uniformity, on/off ratios, and on-current density, while maintaining its performance during ~30% stretching after being mounted on the human skin. In addition, various functional logic gates verified the fidelity of the reported technology, and successful fabrication of non-volatile memory modules with wearable features has been reported for the first time at the time of publication. Second, the networks of semiconducting CNTs were used to fabricate signal amplifiers with a high gain of ~80, which were then used to amplify electrocardiogram (ECG) signals measured using a wearable sensor. At the same time, color-tunable organic light-emitting diodes (CTOLEDs) were developed based on ultra-thin charge blocking layer that controlled the flow of excitons during different voltage regimes. Together, they were integrated to construct a health monitoring platform whereby real-time ECG signals could be detected while simultaneously notifying its user of the ECG status via color changes of the wearable CTOLEDs. Third, intrinsically stretchable CNT transistors were developed, which was enabled by the developments of thickness controllable, vacuum-deposited stretchable dielectric layer and vacuum-deposited metal thin films. Previous works employed strain-tolerant device designs which are based on the use of filamentary serpentine-shaped interconnections, which severely sacrifice the device density. The developed stretchable dielectric, compatible with the current vacuum-based microfabrication technology, exhibited excellent insulating properties even for nanometer-range thicknesses, thereby enabling significant electrical performance improvements such as low operation voltage and high device uniformity/reproducibility, which has not been realized in the most advanced intrinsically stretchable transistors of today.탄소 나노튜브는 뛰어난 전기적, 화학적, 그리고 기계적 특성을 갖고 있어 차세대 유연 전자소자의 핵심 소재 중 하나로 각광을 받고 있으나, 아직까지 이를 이용한 실용적인 유연 전자소자의 개발은 실현되지 않고 있다. 이는 탄소 나노튜브의 전기적 특성대로 완벽히 분류해 낼 수 있는 기술, 탄소 나노튜브를 소자의 원하는 위치에 정확히 원하는 양만큼 네트워크 형태 혹은 정렬된 형태로 증착하는 기술, 그리고 유연 전자소자를 구성하는 다른 물질들의 개발 기술의 부재 때문이다. 지난 10여년간 해당 기술들은 광범위하게 연구되어지고 있으나, 탄소 나노튜브를 활용한 우수한 유연 전자소자 개발을 위한 핵심 기술들의 발전은 아직 초기 단계에 있다. 따라서 이 논문을 통해 탄소 나노튜브를 유연 전자소자에 적용시킬 수 있는 새로운 기술을 소개하고자 한다. 첫번째로 탄소 나노튜브와 유연 전자소자의 소자 디자인을 이용하여 피부위에 증착 가능한 비휘발성 메모리 소자를 제작하였고, 해당 기술을 이용하여 피부위에서 안전하게 동작할 수 있는 다양한 기초 회로들을 구현하였다. 탄소 나노튜브 기반 메모리 전자 소자 및 회로는 다양한 외부 응력이 가해져도 안정적으로 동작을 하였고, 개발된 기술을 통해 보다 실용적인 탄소 나노튜브 기반 유연 전자 소자의 제작 조건을 확립할 수 있었다. 두번째로 위에 개발된 기술을 바탕으로, 보다 복잡한 탄소 나노튜브 기반 유연 회로 및 구동전압에 따라 발광색이 변환하는 색변환 소자를 제작하여 해당 소자들이 피부위에 부착되어 잘 작동되도록 구현하였다. 그리고 이 두 가지 웨어러블 전자소자를 통합하여 실시간으로 심전도를 측정하여 탄소 나노튜브 기반 전자소자를 통해 해당 신호를 증폭시키고, 신호의 상태를 색변환 소자로 나타낼 수 있는 심전도 모니터 시스템을 구현하였다. 세번째로 진공 증착이 가능한 유연 절연체를 개발하여, 기존의 유연 전자소자들이 가지고 있던 극명한 한계를 극복하였다 (높은 구동 전압, 낮은 집적도, 대면적 소자 선능 균일도 등). 기존의 액상 기반 증착을 위주로 한 유연 전자 소자들은 무기물질 기반 전자소자 대비 극심한 성능 저하를 보여주었는데, 이를 해결하기 위해 새로운 절연물질을 개발하고 탄소 나노튜브 기반 유연 전자소자에 적용하여 그 가능성을 보여주었다.Chapter 1. Introduction 1 1.1 Discovery of CNTs and their benefits for soft electronic applications 1 1.2 Electrical sorting of CNTs 5 1.3 Deposition methods of solution-processed semiconducting CNTs 7 1.4 Conclusion 23 1.5 References 24 Chapter 2. Stretchable Carbon Nanotube Charge-Trap Floating-Gate Memory and Logic Devices for Wearable Electronics 32 2.1 Introduction 32 2.2 Experimental section 34 2.3 Results and discussion 36 2.4 Conclusion 62 2.5 References 63 Chapter 3. Wearable Electrocardiogram Monitor Using Carbon Nanotube Electronics and Color-Tunable Organic Light-Emitting Diodes 67 3.1 Introduction 67 3.2 Experimental section 70 3.3 Results and discussion 73 3.4 Conclusion 97 3.5 References 98 Chapter 4. Medium-Scale Electronic Skin Based on Carbon Nanotube Transistors with Vacuum-Deposited Stretchable Dielectric Film 102 4.1 Introduction 102 4.2 Experimental section 106 4.3 Result and discussion 111 4.4 Conclusion 135 4.5 References 136Docto