Testability and redundancy techniques for improved yield and reliability of CMOS VLSI circuits

The research presented in this thesis is concerned with the design of fault-tolerant integrated circuits as a contribution to the design of fault-tolerant systems. The economical manufacture of very large area ICs will necessitate the incorporation of fault-tolerance features which are routinely employed in current high density dynamic random access memories. Furthermore, the growing use of ICs in safety-critical applications and/or hostile environments in addition to the prospect of single-chip systems will mandate the use of fault-tolerance for improved reliability. A fault-tolerant IC must be able to detect and correct all possible faults that may affect its operation. The ability of a chip to detect its own faults is not only necessary for fault-tolerance, but it is also regarded as the ultimate solution to the problem of testing. Off-line periodic testing is selected for this research because it achieves better coverage of physical faults and it requires less extra hardware than on-line error detection techniques. Tests for CMOS stuck-open faults are shown to detect all other faults. Simple test sequence generation procedures for the detection of all faults are derived. The test sequences generated by these procedures produce a trivial output, thereby, greatly simplifying the task of test response analysis. A further advantage of the proposed test generation procedures is that they do not require the enumeration of faults. The implementation of built-in self-test is considered and it is shown that the hardware overhead is comparable to that associated with pseudo-random and pseudo-exhaustive techniques while achieving a much higher fault coverage through-the use of the proposed test generation procedures. The consideration of the problem of testing the test circuitry led to the conclusion that complete test coverage may be achieved if separate chips cooperate in testing each other's untested parts. An alternative approach towards complete test coverage would be to design the test circuitry so that it is as distributed as possible and so that it is tested as it performs its function. Fault correction relies on the provision of spare units and a means of reconfiguring the circuit so that the faulty units are discarded. This raises the question of what is the optimum size of a unit? A mathematical model, linking yield and reliability is therefore developed to answer such a question and also to study the effects of such parameters as the amount of redundancy, the size of the additional circuitry required for testing and reconfiguration, and the effect of periodic testing on reliability. The stringent requirement on the size of the reconfiguration logic is illustrated by the application of the model to a typical example. Another important result concerns the effect of periodic testing on reliability. It is shown that periodic off-line testing can achieve approximately the same level of reliability as on-line testing, even when the time between tests is many hundreds of hours

Impact of Bias Temperature Instability on Soft Error Susceptibility

In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime

ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN

As the MOSFET dimensions scale down towards nanoscale level, the reliability of circuits based on these devices decreases. Hence, designing reliable systems using these nano-devices is becoming challenging. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal (RTS) noise sources to provide a more rigorous noise environment for the simulation of circuits build on nanoscale technologies. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The redesigned MRF is termed as Improved-MRF. The CMOS, MRF and Improved-MRF designs were simulated under application of highly noisy inputs. On the basis of simulations conducted for several test circuits, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives. The number of transistors, on the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF respectively (as compared to the CMOS). Therefore, in order to provide a trade-off between reliability and the area overhead required for obtaining a fault-tolerant circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this research work. The value of RAI exceeds around 1.3 and 40 times for MRF and Improved-MRF respectively as compared to CMOS design which makes Improved- MRF to be still 30 times more efficient circuit design than MRF in terms of maintaining a suitable trade-off between reliability and area-consumption of the circuit

Power supply current [IPS] based testing of CMOS amplifier circuit with and without floating gate input transistors

This work presents a case study, which attempts to improve the fault diagnosis and testability of the power supply current based testing methodology applied to a typical two-stage CMOS operational amplifier and is extended to operational amplifier with floating gate input transistors*. The proposed test method takes the advantage of good fault coverage through the use of a simple power supply current measurement based test technique, which only needs an ac input stimulus at the input and no additional circuitry. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. In the present work, variations of ac ripple in the power supply current IPS, passing through VDD under the application of an ac input stimulus is measured to detect injected faults in the CMOS amplifier. The effect of parametric variation is taken into consideration by setting tolerance limit of ± 5% on the fault-free IPS value. The fault is identified if the power supply current, IPS falls outside the deviation given by the tolerance limit. This method presented can also be generalized to the test structures of other floating-gate MOS analog and mixed signal integrated circuits

Carbon Nanotube Interconnect Modeling for Very Large Scale Integrated Circuits

In this research, we have studied and analyzed the physical and electrical properties of carbon nanotubes. Based on the reported models for current transport behavior in non-ballistic CNT-FETs, we have built a dynamic model for non-ballistic CNT-FETs. We have also extended the surface potential model of a non-ballistic CNT-FET to a ballistic CNT-FET and developed a current transport model for ballistic CNT-FETs. We have studied the current transport in metallic carbon nanotubes. By considering the electron-electron interactions, we have modified two-dimensional fluid model for electron transport to build a semi-classical one-dimensional fluid model to describe the electron transport in carbon nanotubes, which is regarded as one-dimensional system. Besides its accuracy compared with two-dimensional fluid model and Lüttinger liquid theory, one-dimensional fluid model is simple in mathematical modeling and easier to extend for electronic transport modeling of multi-walled carbon nanotubes and single-walled carbon nanotube bundles as interconnections. Based on our reported one-dimensional fluid model, we have calculated the parameters of the transmission line model for the interconnection wires made of single-walled carbon nanotube, multi-walled carbon nanotube and single-walled carbon nanotube bundle. The parameters calculated from these models show close agreements with experiments and other proposed models. We have also implemented these models to study carbon nanotube for on-chip wire inductors and it application in design of LC voltage-controlled oscillators. By using these CNT-FET models and CNT interconnects models, we have studied the behavior of CNT based integrated circuits, such as the inverter, ring oscillator, energy recovery logic; and faults in CNT based circuits