Enabling Solutions for Integration and Interconnectivity in Millimeter-wave and Terahertz Systems

Recently, Terahertz (THz) systems have witnessed increasing attention due to the continuous need for high data rate transmission which is mainly driven by next-generation telecommunication and imaging systems. In that regard, the THz range emerged as a potential domain suitable for realizing such systems by providing a wide bandwidth capable of achieving and meeting the market requirements. However, the realization of such systems faces many challenges, one of which is interconnectivity and high level of integration. Conventional packaging techniques would not be suitable from performance perspective above 100 GHz and new approaches need to be developed. This thesis proposes and demonstrates several approaches to implement interconnects that operate above 100 GHz. One of the most attractive techniques discussed in this work is to implement on-chip coupling structures and insert the monolithic microwave integrated circuit (MMIC) directly into a waveguide (WG). Such approach provides high level of integration and eliminates the need of galvanic contacts; however, it suffers from a major drawback which isthe propagation of parasitic modes in the circuit cavity if the MMIC is large enough to allow such modes to propagate. To mitigate this problem, this work suggests and investigates the use of electromagnetic bandgap (EBG) structures that suppresses those modes such as bed of nails and mushroom-type EBG structures. The proposed techniques are used to implement several on-chip packaging solutions that have an insertion loss as low as 0.6 dB at D-band (110-170 GHz). Moreover, the solutions are demonstrated in several active systems using various commercial MMIC technologies. The thesis also investigates the possibility of utilizing the commercially available packaging technologies such as Embedded Wafer Level Ball Grid Array (eWLB) packaging. Such technology has been widely used for integrated circuits operating below 100 GHz but was not attempted in the THz range before. This work attempts to push the limits of the technology and proposes novel solutions based on coupling structures implemented in the technology’s redistribution layers. The proposed solutions achieve reasonable performance at D-band that are suitable for low-cost mass production while allowing heterogeneous integration with other technologies as well. This work addresses integration challenges facing systems operating in the THz range and proposes high-performance interconnectivity solutions demonstrated in a wide range of commercial technologies and hence enables such systems to reach their full potential and meet the increasing market demands

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Thermal Isolation of High Power Devices in Heterogeneous Integration

Heterogeneous integration (HI) technologies present an important development in the pursuit of higher performance and reduced size, weight, power and cost of electronic systems (SWAP-C). HI systems, however, pose additional challenges for thermal management due to the disparate operating conditions of the devices. If the thermal coupling between devices can be reduced through a strategy of thermal isolation, then the SWAP-C of the accompanying thermal solution can also be reduced. This is in contrast to the alternative scenario of cooling the entire package to the maximum reliable temperature of the most sensitive devices. This isolation strategy must be implemented without a significant increase in device interconnect distances. A counter-intuitive approach is to seek packaging materials of low thermal conductivity – e.g. glass – and enhance them with arrays of metallic through-layer vias. This dissertation describes the first ever demonstration of integrating such via-enhanced interposers with microfluidic cooling, a thermal solution key to the high power applications for which HI was developed. Among the interposers tested, the best performing were shown to exhibit lower thermal coupling than bulk silicon in selective regions, validating their ability to provide thermal isolation. In the course of the study, the via-enhanced interposer is modeled as a thermal metamaterial with desirable, highly-anisotropic properties. Missing from the supporting literature is an accurate treatment of these interposers under such novel environments as microfluidic cooling. This dissertation identifies a new phenomenon, thermal microspreading, which governs how heat couples into a conductive via array from its surroundings. Both finite element analysis (FEA) and a new analytic solution of the associated boundary value problem (BVP) are used to develop a model for describing microspreading. This improves the ability to correctly predict the thermal behavior of via-enhanced interposers under diverse conditions

Développement de briques technologiques pour la co-intégration par l’épitaxie de transistors HEMTs AlGaN/GaN sur MOS silicium

Dans le domaine des semi-conducteurs, la technologie silicium (principalement l’architecture CMOS) répond à la majorité des besoins du marché et, de ce fait, elle est abondamment utilisée. Ce semi-conducteur profite d’une part, de son abondance dans la nature et par conséquent de son faible coût, et d’autre part de la grande maturité de sa technologie qui est étudiée depuis un demi-siècle. Cependant, le silicium (Si) souffre de plus en plus de ses propriétés électriques limitées qui l’excluent de certains domaines dans lesquels les technologies à base de matériaux III-V sont les plus utilisées. Bien que la technologie à base de matériaux III-V, notamment les hétérostructures à base de nitrure de gallium (GaN), soit très performante par rapport à celle à base du matériau historique (le silicium), cette nouvelle technologie est toujours limitée aux applications utilisant des circuits de moyennes voire faibles densités d’intégration. Ceci limite l’utilisation de cette technologie pour la réalisation de produits à très grande valeur ajoutée. Pour s’affranchir de cette limitation, plusieurs sujets de recherche ont été entrepris ces dernières années pour intégrer au sein du même circuit des composants à base de silicium et de matériaux III-V. En effet, la possibilité d’allier les bonnes performances dynamiques de la filière GaN/III-V et la grande densité d’intégration de la technologie Si dans le même circuit constitue une avancée importante avec un potentiel d’impact majeur pour ces deux filières technologiques. L’objectif ciblé par cette nouvelle technologie est la réalisation, sur substrat Si, d’un circuit à base d’hétérostructures GaN de haute performance assurant entre autres, la détection ou l’amplification du signal via des composants III-V tandis que la partie traitement du signal sera réalisée par les circuits CMOS Si. Ce projet de recherche de doctorat s’inscrit directement dans le cadre de l’intégration monolithique d’une technologie HEMT (High Electron Mobility Transistor) à base de matériaux GaN sur CMOS. L’objectif est de développer des architectures compatibles avec la stratégie d’intégration monolithique de transistors HEMTs GaN sur Si, en prenant en compte les exigences des différentes filières, circuits CMOS et croissance/fabrication de structures HEMTs GaN

Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by ∼50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 µA/µm) and Ion up to 40 µA/µm at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only ∼0.01 µm2 footprint, thus increasing both functional density andenergy efficiency

Journal of Telecommunications and Information Technology, 2009, nr 4

kwartalni

Advanced characterisation of novel III-nitride semiconductor based photonics and electronics on polar and non-polar substrates

Advanced characterisation has been carried out on a number of novel III-nitride based photonics and electronics, including micro-LED arrays achieved by a direct epitaxy approach, high performance c-plane HEMTs structure achieved by a novel growth method and non-polar GaN/AlGaN HEMTs. In this work, a systematic study has been conducted to understand the electrical properties of these novel devices, demonstrating their excellent properties. Furthermore, the electrical properties are directly related to epitaxial growth, which provides useful information for further improving device performance, such as 2D growth mode for GaN on a large lattice-mismatched substrate which plays an important in obtaining high breakdown and minimised leakage current for HEMTs. Micro-LEDs are the key elements for a microdisplay system, where electrical properties are extremely important. Potentially, any leakage current can trigger to turn on any neighbouring microLEDs which are supposed to be off. Instead of using conventional fabrication methods which normally enhances leakage current, our team developed a direct epitaxy approach to achieving microLED arrays. In this work, detailed I-V characteristic and capacitance measurements have been conducted on these novel microLED devices, demonstrating leakage currents as low as 14.1 nA per LED and a smooth negative capacitance curve instead of odd positive capacitance performances. Furthermore, a comparison study between our microLEDs and the microLEDs prepared using the conventional method indicates our device shows a large reduction of size-dependent inefficiency while such a behaviour is never observed on the microLEDs fabricated by the conventional methods. Unlike the classic two-step method for GaN growth on large lattice-matched sapphire, our team developed a high-temperature AlN buffer technology, where a 2D growth mode, instead of an initial 2D and then 3D growth mode that typically happens for the growth of conventional GaN growth, takes place through the whole growth process. This method allows us to achieve a breakdown electric field strength of 2.5 MV/cm, a leakage current of as low as 41.7 pA at 20 V and saturation current densities as high as 1.1 A/mm. In this work a systematic study has conducted in order to establish a relationship between the excellent device performance and material properties, where a very low screw dislocation density plays a critical role, while our 2D growth method can provide an excellent opportunity for achieving such a low screw dislocation density. This demonstrates the major advantage over the classic two-step method in the growth of power and RF devices. In our case, we have obtained an unintentional doping as low as 2×10^14 cm-3 and screw dislocation densities of 2.3×10^7 cm-2. Compared with c-plane GaN based HEMTs due to its intrinsic polarisation, non-polar GaN/AlGaN HEMTs on r-plane sapphire yields potential advantages in terms of the fabrication of normal-off devices which are particularly important for practical applications. However, it is a great challenge to achieve high quality non-polar GaN on sapphire. Some initial work has been conducted, where the detailed characterisation indicates an electron mobility of 43 cm2 V-1 s-1 has been initially obtained. Furthermore, instead of using an AlGaN/GaN heterostructure with a modulation doping, we deliberately use a quantum well structure as an electron channel, leading to a mobility of 76 cm2 V-1 s-1. Our simulations as well as measurements also provide a guideline for optimising the general epitaxial structure

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

NASA SBIR abstracts of 1991 phase 1 projects

The objectives of 301 projects placed under contract by the Small Business Innovation Research (SBIR) program of the National Aeronautics and Space Administration (NASA) are described. These projects were selected competitively from among proposals submitted to NASA in response to the 1991 SBIR Program Solicitation. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 301, in order of its appearance in the body of the report. Appendixes to provide additional information about the SBIR program and permit cross-reference of the 1991 Phase 1 projects by company name, location by state, principal investigator, NASA Field Center responsible for management of each project, and NASA contract number are included