Fin Field Effect Transistors Performance in Analog and RF for High-k Dielectrics

The high-k is needed to replace SiO2 as the gate dielectric to reduce the gate leakage current. The impact of a high-k gate dielectric on the device short channel performance and scalability of nanoscale double gate Fin Field Effect Transistors (FinFET) CMOS is examined by 2-D device simulations. DG FinFETs are designed with high-k at the high performance node of the 2008 Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS). DG FinFET CMOS can be optimally designed to yield outstanding performance with good trade-offs between speed and power consumption as the gate length is scaled to < 10 nm. Using technology computer aided design (TCAD) tools a 2-D FinFET device is created and the simulations are performed on it. The optimum value of threshold voltage is identified as VT=0.653V with e=23(ZrO2) for the 2-D device structure. For the 2-D device structure, the leakage current has been reduced to 9.47´10-14 A. High-k improves the Ion/Ioff ratio of transistors for future high-speed logic applications and also improves the storage capability.Defence Science Journal, 2011, 61(3), pp.235-240, DOI:http://dx.doi.org/10.14429/dsj.61.69

Growth Stress Induced Tunability of Dielectric Constant in Thin Films

It is demonstrated here that growth stress has a substantial effect on the dielectric constant of zirconia thin films. The correct combination of parameters - phase, texture and stress - is shown to yield films with high dielectric constant and best reported equivalent oxide thickness of 0.8 nm. The stress effect on dielectric constant is twofold, firstly, by the effect on phase transitions and secondly by the effect on interatomic distances. We discuss and explain the physical mechanisms involved in the interplay between the stress, phase changes and the dielectric constant in detail.Comment: 11 pages, 5 figure

Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators

Improvement in the breakdown endurance of high-κ dielectric by utilizing stacking technology and adding sufficient interfacial layer

Improvement in the time-zero dielectric breakdown (TZDB) endurance of metal-oxide-semiconductor (MOS) capacitor with stacking structure of Al/HfO(2)/SiO(2)/Si is demonstrated in this work. The misalignment of the conduction paths between two stacking layers is believed to be effective to increase the breakdown field of the devices. Meanwhile, the resistance of the dielectric after breakdown for device with stacking structure would be less than that of without stacking structure due to a higher breakdown field and larger breakdown power. In addition, the role of interfacial layer (IL) in the control of the interface trap density (D(it)) and device reliability is also analyzed. Device with a thicker IL introduces a higher breakdown field and also a lower D(it). High-resolution transmission electron microscopy (HRTEM) of the samples with different IL thicknesses is provided to confirm that IL is needed for good interfacial property

Compact modeling of gate tunneling leakage current in advanced nanoscale soi mosfets

En esta tesis se han desarrollado modelos compactos de corriente de fuga por túnel de puerta en SOI MOSFET (de simple y doble puerta) avanzados basados en una aproximación WKB de la probabilidad de túnel. Se han estudiado los materiales dieléctricos high-k más prometedores para los diferentes requisitos de nodos tecnológicos de acuerdo ala hoja de ruta ITRS de miniaturización de dispositivos electrónicos. Hemos presentado un modelo compacto de particionamiento de la corriente de fuga de puerta para un MOSFET nanométrico de doble puerta (DG MOSFET), utilizando modelos analíticos de la corriente de fuga por el túnel directo de puerta. Se desarrollaron también Los modelos analíticos dependientes de la temperatura de la corriente de túnel en la región de inversión y de la corriente túnel asistido por trampas en régimen subumbral. Finalmente, se desarrolló una técnica de extracción automática de parámetros de nuestro modelo compacto en DG MOSFET incluyendo efectos de canal corto. La corriente de la puerta por túnel directo y asistido por trampas modelada mediante los parámetros extraídos se verificó exitosamente mediante comparación con medidas experimentales

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide range of gate-leakage and NBTI stress data from a variety of plasma-oxynitride gate dielectric devices to establish an optimization scheme for gate-leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process and IC design

Ultrathin compound semiconductor on insulator layers for high performance nanoscale transistors

Over the past several years, the inherent scaling limitations of electron devices have fueled the exploration of high carrier mobility semiconductors as a Si replacement to further enhance the device performance. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied, combining the high mobility of III-V semiconductors and the well-established, low cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored. Besides complexity, high defect densities and junction leakage currents present limitations in the approach. Motivated by this challenge, here we utilize an epitaxial transfer method for the integration of ultrathin layers of single-crystalline InAs on Si/SiO2 substrates. As a parallel to silicon-on-insulator (SOI) technology14,we use the abbreviation "XOI" to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsOx layer (~1 nm thick). The fabricated FETs exhibit an impressive peak transconductance of ~1.6 mS/{\mu}m at VDS=0.5V with ON/OFF current ratio of greater than 10,000 and a subthreshold swing of 107-150 mV/decade for a channel length of ~0.5 {\mu}m

Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators