Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures

Eco: A Hardware-Software Co-Design for In Situ Power Measurement on Low-end IoT Systems

Energy-constrained sensor nodes can adaptively optimize their energy consumption if a continuous measurement exists. This is of particular importance in scenarios of high dynamics such as energy harvesting or adaptive task scheduling. However, self-measuring of power consumption at reasonable cost and complexity is unavailable as a generic system service. In this paper, we present Eco, a hardware-software co-design enabling generic energy management on IoT nodes. Eco is tailored to devices with limited resources and thus targets most of the upcoming IoT scenarios. The proposed measurement module combines commodity components with a common system interfaces to achieve easy, flexible integration with various hardware platforms and the RIOT IoT operating system. We thoroughly evaluate and compare accuracy and overhead. Our findings indicate that our commodity design competes well with highly optimized solutions, while being significantly more versatile. We employ Eco for energy management on RIOT and validate its readiness for deployment in a five-week field trial integrated with energy harvesting

NASA Tech Briefs, December 2011

Topics covered include: 1) SNE Industrial Fieldbus Interface; 2) Composite Thermal Switch; 3) XMOS XC-2 Development Board for Mechanical Control and Data Collection; 4) Receiver Gain Modulation Circuit; 5) NEXUS Scalable and Distributed Next-Generation Avionics Bus for Space Missions; 6) Digital Interface Board to Control Phase and Amplitude of Four Channels; 7) CoNNeCT Baseband Processor Module; 8) Cryogenic 160-GHz MMIC Heterodyne Receiver Module; 9) Ka-Band, Multi-Gigabit-Per-Second Transceiver; 10) All-Solid-State 2.45-to-2.78-THz Source; 11) Onboard Interferometric SAR Processor for the Ka-Band Radar Interferometer (KaRIn); 12) Space Environments Testbed; 13) High-Performance 3D Articulated Robot Display; 14) Athena; 15) In Situ Surface Characterization; 16) Ndarts; 17) Cryo-Etched Black Silicon for Use as Optical Black; 18) Advanced CO2 Removal and Reduction System; 19) Correcting Thermal Deformations in an Active Composite Reflector; 20) Umbilical Deployment Device; 21) Space Mirror Alignment System; 22) Thermionic Power Cell To Harness Heat Energies for Geothermal Applications; 23) Graph Theory Roots of Spatial Operators for Kinematics and Dynamics; 24) Spacesuit Soft Upper Torso Sizing Systems; 25) Radiation Protection Using Single-Wall Carbon Nanotube Derivatives; 26) PMA-PhyloChip DNA Microarray to Elucidate Viable Microbial Community Structure; 27) Lidar Luminance Quantizer; 28) Distributed Capacitive Sensor for Sample Mass Measurement; 29) Base Flow Model Validation; 30) Minimum Landing Error Powered-Descent Guidance for Planetary Missions; 31) Framework for Integrating Science Data Processing Algorithms Into Process Control Systems; 32) Time Synchronization and Distribution Mechanisms for Space Networks; 33) Local Estimators for Spacecraft Formation Flying; 34) Software-Defined Radio for Space-to-Space Communications; 35) Reflective Occultation Mask for Evaluation of Occulter Designs for Planet Finding; and 36) Molecular Adsorber Coatin

Scalable processing and integration of 2D materials and devices

Due to its truly two dimensional (2D) character and its particular lattice, single layer graphene (SLG) possesses exceptional properties: it is semimetallic, transparent, strong yet flexible... Complementary features such as the insulating character of hexagonal boron nitride (h-BN) and semiconducting properties of transition metal dichalcogenides (TMDs) enable the whole spectrum of electronic devices to be built with combinations of these 2D materials. Due to this and the ease of exfoliation with a sticky tape, a vast amount of research was sparked. The mechanical exfoliation method, however, is only suitable for novel or proof-of-concept devices. The trend nowadays in electronics is towards transparent, lightweight, flexible, embedded smart devices and sensors in everyday objects such as windows and mirrors, garments, windshields, car seats, parachutes...These demands are already met inherently by these new materials, thus the challenges remaining are within their synthesis, deposition and processing, where more scalable ways of production and device fabrication need to be developed. This thesis explores innovative approaches using established techniques that aim to bridge the gap between proof-of-concept devices and real applications of 2D materials in future commercial level technologies. Methods to create graphene and engineer its properties are employed with a special focus on scalability and adaptability towards the industry. These graphene materials have been processed using pioneering schemes to create different optoelectronic devices and sensors. The techniques employed here for synthesis, transfer and deposition, device processing and characterization of graphene and derivatives, are suitable for their use in large manufacturing and mass-production. Depending on the application envisaged, different materials are used and optimize in order to balance good performance, cost-effectiveness and suitability/scalability of the process for the specific target the device was designed for

NASA Tech Briefs, September 2001

Topics include: special coverage section on sensors, and sections on electronic components systems, software, materials, machinery/automation, manufacturing/fabrication, bio-medical, book and reports, and a special section of Photonics Tech Briefs

A 256-input micro-electrode array with integrated cmos amplifiers for neural signal recording

Thesis (Ph.D.)--Boston UniversityThe nervous system communicates and processes information through its basic structural units -- individual neurons (nerve cells). Neurons convey neural information via electrical and chemical signals, which makes electrophysiological recording techniques very important in the study of neurophysiology. Specifically, active microelectrode arrays (MEAs) with amplifiers integrated on the same substrate are used because they provide a very powerful neural electrical recording technique that can be directly interfaced to acute slices and cell cultures. 2D planer electrodes are typically used for recording from neural cultures in vitro, while in vivo recording in live animals invariably requires the use of 3D electrodes. I have designed an active MEA with neural amplifiers and 3D electrodes, all integrated on a single chip. The electrodes are commercially available 3D C4 (Controlled Collapse Chip Connect) flip-chip bonding solder balls that have a diameter of 100 µm and a pitch of 200 µm. An active MEA neural recording chip -- the Multiple-Input Neural Sensor (MINS) chip -- was designed and fabricated using the IBM BiCMOS 8HP 0.13 µm technology. The MINS IC has 256 input channels that are time-division multiplexed into two output pads. Each channel was designed to work at a 20 kHz frame rate with a total voltage gain of 60 dB per channel with an input-referred noise voltage of 5.3 µVrms over 10 Hz to 10 kHz. The entire MINS chip has an area of 4 x 4 mm^2 with 256 input C4s plus 20 wire-bond pads on two adjacent edges of the chip for power, control, and outputs. The fabricated MINS chips are wire-bonded to standard pin grid array (PGA), open-top PGA, and custom-designed printed circuit board (PCB) packages for electrical, in vitro, and in vivo testing, respectively. After process variation correction, the voltage gain of the 256 neural amplifiers, measured in vitro across several chips, has a mean value of 58.7 dB and a standard deviation of 0.37 dB. Measurements done with the electrical testing package demonstrate that the MINS IC has a flat frequency response from 0.05 Hz to 1.4 MHz, an input-referred noise voltage of 4.6 µVrms over 10 Hz to 10 kHz, an output voltage swing as large as 1.5 V peak-to-peak, and a total power consumption of 11.25 mW, or 43.9 µW per input channel

Why High-Performance Modelling and Simulation for Big Data Applications Matters

Modelling and Simulation (M&S) offer adequate abstractions to manage the complexity of analysing big data in scientific and engineering domains. Unfortunately, big data problems are often not easily amenable to efficient and effective use of High Performance Computing (HPC) facilities and technologies. Furthermore, M&S communities typically lack the detailed expertise required to exploit the full potential of HPC solutions while HPC specialists may not be fully aware of specific modelling and simulation requirements and applications. The COST Action IC1406 High-Performance Modelling and Simulation for Big Data Applications has created a strategic framework to foster interaction between M&S experts from various application domains on the one hand and HPC experts on the other hand to develop effective solutions for big data applications. One of the tangible outcomes of the COST Action is a collection of case studies from various computing domains. Each case study brought together both HPC and M&S experts, giving witness of the effective cross-pollination facilitated by the COST Action. In this introductory article we argue why joining forces between M&S and HPC communities is both timely in the big data era and crucial for success in many application domains. Moreover, we provide an overview on the state of the art in the various research areas concerned