52 research outputs found
Electronically Tunable Current-Mode Third-Order Square-Root-Domain Filter Design
In this study, electronically-tunable, current-mode, square-root-domain, third-order low-pass filter is proposed. The study is carried out with three circuit designs. First circuit is third-order low-pass Butterworth filter, second circuit is third-order low-pass Chebyshev filter and the last circuit is third-order low-pass elliptic filter. All the input and output values of the filter circuit are current. Only grounded capacitors and MOSFETs are required in order to realize the filter circuit. Additionally, natural frequency f0 of the current-mode filter can be adjusted electronically using outer current sources. To validate the theory and to demonstrate the performance of third-order filter, frequency and time domain simulations of PSPICE program are used. To that end, TSMC 0.35μm Level 3 CMOS process parameters are utilized to realize the simulations of the filter. © 2018 World Scientific Publishing Company
Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers
In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level.
At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs.
At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers.
The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007
CMOS Hyperbolic Sine ELIN filters for low/audio frequency biomedical applications
Hyperbolic-Sine (Sinh) filters form a subclass of Externally-Linear-Internally-Non-
Linear (ELIN) systems. They can handle large-signals in a low power environment under half
the capacitor area required by the more popular ELIN Log-domain filters. Their inherent
class-AB nature stems from the odd property of the sinh function at the heart of their
companding operation. Despite this early realisation, the Sinh filtering paradigm has not
attracted the interest it deserves to date probably due to its mathematical and circuit-level
complexity.
This Thesis presents an overview of the CMOS weak inversion Sinh filtering
paradigm and explains how biomedical systems of low- to audio-frequency range could
benefit from it. Its dual scope is to: consolidate the theory behind the synthesis and design of
high order Sinh continuous–time filters and more importantly to confirm their micro-power
consumption and 100+ dB of DR through measured results presented for the first time.
Novel high order Sinh topologies are designed by means of a systematic
mathematical framework introduced. They employ a recently proposed CMOS Sinh
integrator comprising only p-type devices in its translinear loops. The performance of the
high order topologies is evaluated both solely and in comparison with their Log domain
counterparts. A 5th order Sinh Chebyshev low pass filter is compared head-to-head with a
corresponding and also novel Log domain class-AB topology, confirming that Sinh filters
constitute a solution of equally high DR (100+ dB) with half the capacitor area at the expense
of higher complexity and power consumption. The theoretical findings are validated by
means of measured results from an 8th order notch filter for 50/60Hz noise fabricated in a
0.35μm CMOS technology. Measured results confirm a DR of 102dB, a moderate SNR of
~60dB and 74μW power consumption from 2V power supply
Single-input Multiple-output Tunable Log-domain Current-mode Universal Filter
This paper describes the design of a current-mode single-input multiple-output (SIMO) universal filter based on the log-domain filtering concept. The circuit is a direct realization of a first-order differential equation for obtaining the lossy integrator circuit. Lossless integrators are realized by log-domain lossy integrators. The proposed filter comprises only two grounded capacitors and twenty-four transistors. This filter suits to operate in very high frequency (VHF) applications. The pole-frequency of the proposed filter can be controlled over five decade frequency range through bias currents. The pole-Q can be independently controlled with the pole-frequency. Non-ideal effects on the filter are studied in detail. A validated BJT model is used in the simulations operated by a single power supply, as low as 2.5 V. The simulation results using PSpice are included to confirm the good performances and are in agreement with the theory
Realization of Integrable Low- Voltage Companding Filters for Portable System Applications
Undoubtedly, today’s integrated electronic systems owe their remarkable performance
primarily to the rapid advancements of digital technology since 1970s. The various
important advantages of digital circuits are: its abstraction from the physical details of
the actual circuit implementation, its comparative insensitiveness to variations in the
manufacturing process, and the operating conditions besides allowing functional
complexity that would not be possible using analog technology. As a result, digital
circuits usually offer a more robust behaviour than their analog counterparts, though
often with area, power and speed drawbacks. Due to these and other benefits, analog
functionality has increasingly been replaced by digital implementations.
In spite of the advantages discussed above, analog components are far from
obsolete and continue to be key components of modern electronic systems. There is
a definite trend toward persistent and ubiquitous use of analog electronic circuits in
day-to-day life. Portable electronic gadgets, wireless communications and the
widespread application of RF tags are just a few examples of contemporary
developments. While all of these electronic systems are based on digital circuitry,
they heavily rely on analog components as interfaces to the real world. In fact, many
modern designs combine powerful digital systems and complementary analog
components on a single chip for cost and reliability reasons. Unfortunately, the design
of such systems-on-chip (SOC) suffers from the vastly different design styles of
analog and digital components. While mature synthesis tools are readily available for
digital designs, there is hardly any such support for analog designers apart from wellestablished
PSPICE-like circuit simulators. Consequently, though the analog part
usually occupies only a small fraction of the entire die area of an SOC, but its design
often constitutes a major bottleneck within the entire development process.
Integrated continuous-time active filters are the class of continuous-time or
analog circuits which are used in various applications like channel selection in radios,
anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a
filter is the dynamic range; this is the ratio of the largest to the smallest signal that can
be applied at the input of the filter while maintaining certain specified performance.
The dynamic range required in the filter varies with the application and is decided by
the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the
capacitor area of an integrated active filter increases in proportion to its dynamic
range. This situation is incompatible with the needs of integrated systems, especially
battery operated ones. In addition to this fundamental dependence of power dissipation
on dynamic range, the design of integrated active filters is further complicated by the
reduction of supply voltage of integrated circuits imposed by the scaling down of
technologies to attain twin objective of higher speed and lower power consumption in
digital circuits. The reduction in power consumption with decreasing supply voltage
does not apply to analog circuits. In fact, considerable innovation is required with a
reduced supply voltage even to avoid increasing power consumption for a given signal
to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer.
A technique which has attracted the attention of circuit designers as a possible
route to filters with higher dynamic range per unit power consumption is
“companding”. Companding (compression-expansion) filters are a very promising
subclass of continuous-time analog filters, where the input (linear) signal is initially
compressed before it will be handled by the core (non-linear) system. In order to
preserve the linear operation of the whole system, the non-linear signal produced by
the core system is converted back to a linear output signal by employing an
appropriate output stage. The required compression and expansion operations are
performed by employing bipolar transistors in active region or MOS transistors in
weak inversion; the systems thus derived are known as logarithmic-domain (logdomain)
systems. In case MOS transistors operated in saturation region are employed,
the derived structures are known as Square-root domain systems. Finally, the third
class of companding filters can also be obtained by employing bipolar transistors in
active region or MOS transistors in weak inversion; the derived systems are known as
Sinh-domain systems. During the last several years, a significant research effort has been already
carried out in the area of companding circuits. This is due to the fact that their main
advantages are the capability for operation in low-voltage environment and large
dynamic range originated from their companding nature, electronic tunability of the
frequency characteristics, absence of resistors and the potential for operations in varied
frequency regions.Thus, it is obvious that companding filters can be employed for implementing
high-performance analog signal processing in diverse frequency ranges. For example,
companding filters could be used for realizing subsystems in: xDSL modems, disk
drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked
loops, FM stereo demodulator, touch-tone telephone tone decoder and
crossover network used in a three-way high-fidelity loudspeaker etc.
A number of design methods for companding filters and their building blocks
have been introduced in the literature. Most of the proposed filter structures operate
either above 1.5V or under symmetrical (1.5V) power supplies. According to data that
provides information about the near future of semiconductor technology, International
Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital
circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of
analog integrated circuits is the usage of low-voltage building blocks that use a single
0.5-1.5V power supply.
Therefore, the present investigation was primarily concerned with the study and
design of low voltage and low power Companding filters. The work includes the
study about: the building blocks required in implementing low voltage and low power
Companding filters; the techniques used to realize low voltage and low power
Companding filters and their various areas of application.
Various novel low voltage and low power Companding filter designs have been
developed and studied for their characteristics to be applied in a particular portable
area of application. The developed designs include the N-th order universal
Companding filter designs, which have been reported first time in the open literature.
Further, an endeavor has been made to design Companding filters with orthogonal
tuning of performance parameters so that the designs can be simultaneously used for
various features. The salient features of each of the developed circuit are described.
Electronic tunability is one of the major features of all of the designs. Use of
grounded capacitors and resistorless designs in all the cases makes the designs suitable
for IC technology. All the designs operate in a low-voltage and low-power
environment essential for portable system applications.
Unless specified otherwise, all the investigations on these designs are based on the
PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The
performance of each circuit has been validated by comparing the characteristics
obtained using simulation with the results present in the open literature.
The proposed designs could not be realized in silicon due to non-availability of
foundry facility at the place of study. An effort has already been started to realize
some of the designs in silicon and check their applicability in practical circuits. At the
basic level, one of the proposed Companding filter designs was implemented using the
commercially available transistor array ICs (LM3046N) and was found to verify the
theoretical predictions obtained from the simulation results
A very compact KHN filter with multidecade tuning
A very compact implementation of a multifunction
Kerwin Huelsman Newcomb (KHN) filter that can be frequency
tuned almost seven decades, from 0.2 Hz to 1 Mhz, is presented.
Tuning is achieved by means of high-value, programmable
active resistors biased using the quasi floating gate (QFG)
technique and linearisated through capacitive gate voltage
averaging. The circuit, realized in a 0.5 μm standard CMOS
technology using only four CMOS inverters, six small
capacitors, six small resistors and two programmable active
resistors, occupies a total area of 0.02 mm2, dissipates 3.45 mW
and presents a dynamic range at 0.1 % THD of 55.86
A Novel Square Root Domain Lossless Integrator and Its Application to KHN Biquad Filter Design
Abstract In this paper, a novel square root domain lossless integrator and its application to KHN (Kerwin-HuelsmanNewcomb) biquad are proposed. The presented lossless integrator based on quadratic characteristics of MOS transistor was designed by using state space method. It consists of a geometric mean circuit, a current mirror and a capacitor. The scaling factor of the integrator is electronically tuneable by an external bias current. The KHN biquad consists of two lossless integrator blocks and a summer circuit. The summer circuit is developed by using linear transconductors. KHN biquad filter was simulated by using SPICE simulation program, simulation results are good in agreement with the theoretical analysis
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