CMOS Low-Noise Amplifier Design for Reconfigurable Mobile Terminals

Kommunikationsstandards aus Europa, Japan und den USA sind mit einander nicht kompatibel. Das ist einen Nachteil besonders in der Mobiltelefonie, wo es bisher keinen allgemeinen Standard gibt. Die Vielzahl an Funkstandards führt zu einigen Nachteilen, deshalb scheint das Bedürfnis für Rekonfigurierbarkeit offensichtlich zu sein. Ein rekonfigurierbares Terminal sollte im Stande sein, verschiedene Standards zu unterstützen. Die vernünftige Integration von verschiedenen Standards kann Standards einschließen, die derselben Familie (z.B. GSM) gehören, aber in verschiedenen Kontinenten entwickelt werden. Solche Terminals existieren bereits und ein breites Angebot besteht auf dem Markt. Ein ziemlich neuer Ansatz der Standardintegration ist die Kombination von verschiedenen Familien von Standards, zum Beispiel zwischen drahtloser Datenübertragung wie UMTS mit WLAN oder HIPERLAN. In diesem Fall sind fast alle Parameter, die einen Standard definieren, verschieden. In dieser Arbeit wird ein rekonfigurierbares Multistandard Terminal betrachtet, das sowohl OFDM basierte WLAN Standards (IEEE802.11 und Hiperlan/2) als auch den CDMA basierten UMTS FDD unterstützt. Besondere Aufmerksamkeit galt dem Empfänger dieses Terminals. Eine rekonfigurierbare hybride Architektur ist ausstelle einer Architektur entwickelt worden, die mehrere Parallele umschaltbare Sender-Empfänger verwendet. Zusätzlich zur hybriden Architektur werden die negativen Einflüsse des HF-Teils auf die Empfänger-Performance untersucht. Der zweite Teil dieser Arbeit behandelt Transistor-Physik und den Entwurf eines rauscharmen Verstärkers für einen rekonfigurierbaren Empfänger, wie oben beschrieben. Da die kleinen FET-Größen aktuellen submikrometer RF-MOS-Technologien niedrige Kapazitätswerte haben, sind große Induktivitäten für die Anpassung erforderlich. Wegen ihre großen Abmessungen werden sie außerhalb des ICs realisiert. Deshalb kann die Pad-Kapazität im Designprozess nicht länger vernachlässigt werden. Es wird gezeigt, dass die Rauschzahl von rauscharmen Verstärkern wesentlich durch die richtige Wahl von passiven Systemkomponenten verbessert werden kann. Eine Designmethodik wird eingeführt, die den equivalenten Rauschwiderstand reduziert, und dadurch sehr gutes Rauschverhalten trotz relativ schlechte Rauschanpassung erreichen kann. Die Messungen des Verstärkers hinsichtlich Rauschverhalten und Stromverbrauch, zeigen sehr gute Ergebnisse. Sie gehören zu den besten überhaupt bekannten. 0.76 dB-Rauschzahl und 12 dB Gewinn wurden bei 2.14 GHz erreicht, bei 3.5 mA Stromverbrauch und 1.2V Betriebsspannung.Communication standards developed in Europe, Japan and USA are not compatible with each other. This is a profound drawback particularly in the digital cellular telephony, where there is no common standard up to now. The variety of wireless standards leads to some disadvantages, therefore the need for reconfigurability seems to be evident. A reconfigurable terminal should be able to support different standards. Reasonable integration of different standards may include standards, which belong to the same family (e.g., GSM), but are developed in different continents. Such terminals have been already produced and a broad offer exists on the market. A rather new approach of the standard integration is the combination of different families of standards, for example between wireless data and digital cellular telephony like UMTS with WLAN or HIPERLAN. In this case, nearly all parameters defining a standard are different. In the scope of this work the multistandard, reconfigurable terminal is considered that supports the OFDM based WLAN standards (IEEE802.11 and Hiperlan/2) and the CDMA based UMTS FDD standard. Special consideration has been made for the receiver of this terminal. A reconfigurable hybrid architecture has been developed, rather than an architecture using many parallel switchable transceivers. Additionally to the hybrid architecture, a study on RF impairments is given. The second part of this work handles with transistor physics and low noise amplifier design for a reconfigurable receiver, defined earlier. Since the small FET sizes of state of the art sub-micron RF-MOS-technologies have low capacitance values, thus large inductors are needed for matching. Because of theirs large dimensions they are placed off-chip. For this reason, the pad capacitance can not be longer neglected in the design process. % It is shown that the noise figure of low-noise amplifiers can be improved considerably by a proper choice of passive components. A design methodology is introduced, which reduces the equivalent noise resistance, and thus very good noise performance can be achieved in spite of rather poor noise matching. The measurements of the amplifier, in respect to the noise performance and power consumption, show very good results, one of the best ever reported. 0.76 dB noise figure and 12 dB gain were achieved at 2.14~GHz, 3.5 mA supply current and 1.2 V supply voltage

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

Design issues and experimental characterization of a continuously-tuned adaptive CMOS LNA

This paper presents the design implementation and experimental characterization of an adaptive Low Noise Amplifier (LNA) intended for multi-standard Radio Frequency (RF) wireless transceivers. The circuit —fabricated in a 90-nm CMOS technology— is a two-stage inductively degenerated common-source topology that combines PMOS varactors with programmable load to make the operation of the circuit continuously tunable. Practical design issues are analyzed, considering the effect of circuit parasitics associated to the chip package and integrated inductors, capacitors and varactors. Experimental measurements show a continuous tuning of NF and Sparameters within the 1.75-2.23GHz band, featuring NF19.6dB and IIP3> −9.8dBm, with a power dissipation < 23mW from a 1-V supply voltage.Ministerio de Ciencia e Innovación (FEDER) TEC2007-67247-C02-01/MICJunta de Andalucía, Consejo Regional de Innovación, ciencia y empresa TIC-253

0.5V 3rd-order Tunable gm-C Filter

This paper proposes a 3rd-order gm-C filter that operates with the extremely low voltage supply of 0.5V. The employed transconductor is capable for operating in an extremely low voltage power supply environment. A benefit offered by the employed transconductor is that the filter’s cut-off frequency can be tuned, through a dc control current, for relatively large ranges. The filter structure was designed using normal threshold transistors of a triple-well 0.13μm CMOS process and is operated under a 0.5V supply voltage; its behavior has been evaluated through simulation results by utilizing the Analog Design Environment of the Cadence software

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band

Design of a Cost-Efficient Reconfigurable Pipeline ADC

Power budget is very critical in the design of battery-powered implantable biomedical instruments. High speed, high resolution and low power usually cannot be achieved at the same time. Therefore, a tradeoff must be made to compromise every aspect of those features. As the main component of the bioinstrument, high conversion rate, high resolution ADC consumes most of the power. Fortunately, based on the operation modes of the bioinstrument, a reconfigurable ADC can be used to solve this problem. The reconfigurable ADC will operate at 10-bit 40 MSPS for the diagnosis mode and at 8-bit 2.5 MSPS for the monitor mode. The ADC will be completely turned off if no active signal comes from sensors or if an off command is received from the antenna. By turning off the sample hold stage and the first two stages of the pipeline ADC, a significant power saving is achieved. However, the reconfigurable ADC suffers from two drawbacks. First, the leakage signals through the extra off-state switches in the third stage degrade the performance of the data converter. This situation tends to be even worse for high speed and high-resolution applications. An interference elimination technique has been proposed in this work to solve this problem. Simulation results show a significant attenuation of the spurious tones. Moreover, the transistors in the OTA tend to operate in weak inversion region due to the scaling of the bias current. The transistor in subthreshold is very slow due to the small transit frequency. In order to get a better tradeoff between the transconductance efficiency and the transit frequency, reconfigurable OTAs and scalable bias technique are devised to adjust the operating point from weak inversion to moderate inversion. The figure of merit of the reconfigurable ADC is comparable to the previously published conventional pipeline ADCs. For the 10-bit, 40 MSPS mode, the ADC attains a 56.9 dB SNDR for 35.4 mW power consumption. For the 8-bit 2.5 MSPS mode, the ADC attains a 49.2 dB SNDR for 7.9 mW power consumption. The area for the core layout is 1.9 mm2 for a 0.35 micrometer process

Analysis and Design of Wideband Low Noise Amplifier with Digital Control

The design issues in designing low noise amplifier (LNA) for Software-Defined-Radio (SDR) are reviewed. An inductor-less wideband low noise amplifier aiming at low frequency band (0.2-2GHz) for Software-Defined-Radio is presented. Shunt-shunt LNA with active feedback is used as the first stage which is carefully optimized for low noise and wide band applications. A digitally controlled second stage is employed to provide an additional 12dB gain control. A novel method is proposed to bypass the first stage without degrading input matching. This LNA is fabricated in a standard 0.18 um CMOS technology. The measurement result shows the proposed LNA has a gain range of 6dB-18dB at high gain mode and -12dB-0dB at low gain mode, as well as a –3dB bandwidth of 2GHz. The noise figure (NF) is 3.5-4.5dB in the high gain setting mode. It consumes 20mW from a 1.8V supply

Nonvolatile CMOS memristor, reconfigurable array and its application in power load forecasting

© 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This is the accepted manuscript version of a conference paper which has been published in final form at https://doi.org/10.1109/TII.2023.3341256The high cost, low yield, and low stability of nano-materials significantly hinder the application and development of memristors. To promote the application of memristors, researchers proposed a variety of memristor emulators to simulate memristor functions and apply them in various fields. However these emulators lack nonvolatile characteristics, limiting their scope of application. This paper proposes an innovative nonvolatile memristor circuit based on complementary metal-oxide-semiconductor (CMOS) technology, expanding the horizons of memristor emulators. The proposed memristor is fabricated in a reconfigurable array architecture using the standard CMOS process, allowing the connection between memristors to be altered by configuring the on-off state of switches. Compared to nano-material memristors, the CMOS nonvolatile memristor circuit proposed in this paper offers advantages of low manufacturing cost and easy mass production, which can promote the application of memristors. The application of the reconfigurable array is further studied by constructing an Echo State Network (ESN) for short-term load forecasting in the power system.Peer reviewe