This paper presents the design implementation and experimental characterization of an adaptive Low Noise Amplifier (LNA) intended for multi-standard Radio Frequency (RF) wireless transceivers. The circuit —fabricated in a 90-nm CMOS technology— is a two-stage inductively degenerated common-source topology that combines PMOS varactors with programmable load to make the operation of the circuit continuously tunable. Practical design issues are analyzed, considering the effect of circuit parasitics associated to the chip package and integrated inductors, capacitors and varactors. Experimental measurements show a continuous tuning of NF and Sparameters within the 1.75-2.23GHz band, featuring NF19.6dB and IIP3> −9.8dBm, with a power dissipation < 23mW from a 1-V supply voltage.Ministerio de Ciencia e Innovación (FEDER) TEC2007-67247-C02-01/MICJunta de Andalucía, Consejo Regional de Innovación, ciencia y empresa  TIC-253

Becerra Álvarez, Edwin C.

Rosa Utrera, José Manuel de la

Sandoval Ibarra, F.

English

idUS. Depósito de Investigación Universidad de Sevilla

Design Issues and Experimental Characterization ofa Continuously-Tuned Adaptive CMOS LNAEdwin C. Becerra-Alvarez, Jose M. de la RosaInstituto de Microelectronica de Sevilla, IMSE-CNM(CSIC/Universidad de Sevilla)C/Americo Vespucio, 41092 Sevilla, SPAINE-mail: [edwin,jrosa]@imse-cnm.csic.esFederico Sandoval-IbarraCINVESTAV-Unidad GuadalajaraAv. Cientifica No. 1145, 45015Col. El Bajio, Zapopan, Jalisco, MEXICOE-mail: sandoval@gdl.cinvestav.mxAbstract—This paper presents the design implementation andexperimental characterization of an adaptive Low Noise Am-plifier (LNA) intended for multi-standard Radio Frequency(RF) wireless transceivers. The circuit —fabricated in a 90-nm CMOS technology— is a two-stage inductively degeneratedcommon-source topology that combines PMOS varactors withprogrammable load to make the operation of the circuit contin-uously tunable. Practical design issues are analyzed, consideringthe effect of circuit parasitics associated to the chip packageand integrated inductors, capacitors and varactors. Experimen-tal measurements show a continuous tuning of NF and S-parameters within the 1.75-2.23GHz band, featuring NF<3.7dB,S21 >19.6dB and IIP3> −9.8dBm, with a power dissipation <23mW from a 1-V supply voltage. 1I. INTRODUCTIONThe integration of increasingly complex Radio Frequency(RF) front-end circuits into mainstream nanometer CMOStechnologies imposes a number of challenges and trade-offsthat makes their design a key issue to guarantee the quality ofservice of the resulting wireless hand-held terminals. Amongother RF building blocks, the design of the Low NoiseAmplifier (LNA) is particularly critical due to its early positionat the very beginning of the receiver chain, what makes thiscircuit a limiting factor in the overall system performance [1].The difficulty of designing nanometer CMOS LNAs isaggravated in the case of multi-standard applications, in whichthese circuits must operate over different frequency ranges,whereas keeping reduced number of passive circuit elementsto increase integration [2]. As a consequence, most reportedmulti-standard LNAs increase the number of integrated passiveelements (basically capacitors and inductors) as compared totheir mono-standard counterparts [3]–[5]. Therefore, the sili-con area – mainly occupied by those elements – is not clearlyreduced as compared to using switchable mono-standard LNAs[6].The work in this paper contributes to this topic and presentsthe practical implementation and experimental measurementsof a continuously reconfigurable CMOS LNA. The circuit1This work has been supported by the Spanish Ministry of Science andInnovation (with support from the European Regional Development Fund)under contract TEC2007-67247-C02-01/MIC, and the Regional Council ofInnovation, Science and Enterprise under contract TIC-2532.adapts its performance to the requirements of different stan-dards without increasing the number of inductors as comparedto a typical mono-standard LNA. It employs a two-stagetopology with programmable load to separately control theinput impedance, Noise Figure (NF) and signal gain. A PMOS-varactor based tuning network is used in both stages in orderto make the resonance frequency continuously programmablewithout penalizing the LNA noise performance. Experimentalmeasurements demonstrate a correct operation of the circuit.II. LNA TOPOLOGY AND CIRCUIT ANALYSISFig. 1 shows the complete schematic of the proposedLNA, which consists of a two-stage topology with separatetuning networks. The input stage is an inductively degeneratedcommon-source structure — using bonding inductor Ls— toprovide a specified real part for the input impedance and signalgain at a given frequency. Programmable biasing is used toseparately control the real part of the load of both stages,implemented by transistors MpNF2 and MpGAIN2. In thisway, NF and forward gain, S21 , can be individually con-trolled by diode-connected transistors MpNF1 and MpGAIN1,respectively. Thus, the drain current of these transistors, IbNFand IbGAIN, are adapted to properly biasing the gate ofMpNF2 and MpGAIN2, with reduced power dissipation.The noise factor (F) and input impedance, Zin, of the LNAare approximately given by [1]:BondingBondingCI COCgClininductanceIbGAINIbNFLdLgLlLOLsMn1Mn2MpGAIN1 MpGAIN2MpNF1 MpNF2outPAD PADPAD PADPADPADsProgrammable LoadRb1Rb2RGAINRNFVTIVTOFig. 1. Schematic of the proposed adaptive LNA.F ! 1 +(ω0γωTαQ)[1− 2|c|Q√δα25γ+(δα25γ)(1 +Q2)](1)Zin !CI + Cgsn1sCICgsn1+s(Lg+Ls)+ωTLs [1− sωTLsCg] (2)whereα ! gmn1gdsn1Q ! ωTω0RRF gmn1ω0 ! 1√Cgsn1(Lg + Ls)ωT ! gmn1Cgsn1(3)with c being the correlation factor; δ and γ are technologyparameters; RRF is the RF source resistance; gdsn1, gmn1 andCgsn1 are respectively the small-signal drain-source conduc-tance, transconductance and gate-source capacitance of Mn1.The tuning mechanism of the LNA is achieved by varyingthe resonance frequencies of the passive input- and output-tuning networks, respectively given by:win !1√Cgsn1[Lg + Ls − (ωTLs)2 Cg] (4)wout !1√LlCl(5)where Cg and Cl are implemented by accumulation PMOSvaractors.III. PRACTICAL DESIGN ISSUESThe above analysis assumed ideal circuit elements, partic-ularly varactors and inductors. In practice, circuit parasiticscause these elements to behave as RLC filters that mayseverely degrade the performance of the LNA [1]. This isspecially important in the case of reconfigurable/adaptive RFcircuits like the one reported in this paper, because of the manydifferent specifications to be covered by the same circuit.A. Analysis of Circuit ParasiticsIn order to evaluate the impact of circuit parasitics, mainfigures were analyzed replacing every inductor and varactorwith the equivalent circuit shown in Fig. 2 [1]. As a result, amore realistic expression for the input impedance is found,Zin !ZCgZ3lgZib+Z3lg(sCIZCg + 1) + ZCgZ2lgsCI(6)whereZib ! 1sCgsn1+ (ωT + 1)sLsZ2lg ! R5g + 1sC5gZCg ! 2R7g + 1s(Ccg + Cpg)Z3lg ! R1g + sL3g1 + sC2g(R1g + sL3g)(7)C1 C5C3C2 C4L3 L4R3 R5R4R1 R2vi vo(a)CcCpL1 L2R7R6 Rwvi vo(b)Fig. 2. Equivalent RLC circuit for (a) inductors and (b) varactors.Replacing the inductors and varactors in Fig. 1 with thecircuits shown in Fig. 2, the expression of S21 results in:S21 !(4gmn1Z2lgZ1ldZCgsLsgmn1Z21ld + s2Cgsn2LsZ1ldZCg)·(gmn2RLZ1loZ2llZCl2Z21loZ2llZCl + Z2ll(RL + ZCg)) (8)whereZ1ld ! R3d + 1sC1dZ1lo ! R3o + 1sC1oZ2ll ! R5l + 1sC5lZCl ! 2R7l + 1s(Ccl + Cpl)(9)RL is the load resistance; gmn2 and Cgsn2 are respectively thesmall-signal transconductance and gate-source capacitance ofMn2.B. Chip package parasiticsThe above expressions have been used in combination withelectrical simulations using Cadence SpectreRF to design theLNA. For that purpose, the circuit in Fig. 3 was used. Thiscircuit includes the package and the external components tobe included in the PCB. A 4mmx4mm 12-pin QFN plasticpackage has been used. This package has been modeledusing Cadence PKG tool in order to take into account theirassociated parasitics during the design process.IV. EXPERIMENTAL RESULTSThe LNA has been designed to fulfill the requirements of amulti-standard wireless direct-conversion receiver consideringa continuously-tuned operating frequency within the 1.75-2.23GHz band. The circuit was implemented using a 90-nm CMOStechnology with a single 1-V supply voltage. Fig. 4(a) showsa microphotograph of the chip highlighting their main parts,in outPADPINPIN rightPIN leftRGAINRNFVDDVDDVTIVTOFig. 3. Equivalent circuit of the chip package.namely integrated inductors, capacitors, PMOS varactors andCMOS active area. Integrated inductors have octagonal shapewith a patterned ground shield. Input/output capacitors areimplemented by M-O-M structures, which are based on thecombination of stacked and finger metal-metal capacitors. Allpads are Electrostatic Discharged (ESD) protected. The diearea, including pads, is 1.8 mm2, with the core occupying 1.0mm2. As usual, a significant portion of this area is used byintegrated inductors. However, in this circuit, and contrary tomost reported multi-standard LNAs, the number of inductorsis not increased as compared to the mono-standard case, withthe subsequent area saving. The chip has been tested using thePCB shown in Fig. 4(b), that includes the necessary filteringfor biasing and power supplies as well as off-chip resistorsand connectors for the instruments.Fig. 5 shows the measured NF vs. input frequency corre-sponding to different values of tuned frequencies, demonstrat-ing the reconfigurability capability of the proposed circuit witha programmable NF within the band of interest. The overallminimum value is 2.5dB, obtained at 1GHz.Reconfiguration ofS-parameters is illustrated in Fig. 6, whereas input reflectioncoefficient, S11 (Fig. 6(a)) and forward gain, S21 (Fig. 6(b))are shown. The value of S21 varies from 19.8dB at 2.23GHzto 23.4dB at 1.9GHz, whereas S11 is always below −10dB.Note that —although not shown in Fig. 6 for the sake ofclarity— the operation of the circuit can be continuously tunedwithin the band of interest, 1.75-2.23GHz. This feature is adirect consequence of using PMOS varactors in the resonanttank, providing approximately 500-MHz tuning range. Indeed,this is a peculiarity of the presented chip as compared topreviously reported multi-standard LNAs, mostly based onusing switchable LC tanks to select the operating frequency ina discrete way and using varactors to fine tuning the selectedband. On the contrary, the proposed LNA achieves a coarsecontinuous frequency tuning capability, just using varactors.Indeed, this is a first step towards using a tuning frequencyrange of several GHz —required in future software radios.The operation of the circuit has been tested for a couple ofstandard specifications within the band of interest, namely:GSM and WCDMA. As an illustration, Fig. 7 shows S-parameters for both standards, highlighting the values at thecenter frequency of each standard band.Finally, Table I sums up the measured performance of theActive areaCgClCICOLdLgLlLo(a)LNA chip(b)Fig. 4. (a) Chip Microphotograph and (b) PCB.0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.62.533.544.555.56 2.5 dBTuning FrequencyFreq. (GHz)NF(dB)Fig. 5. NF reconfiguration.LNA by showing their main figures of merit. This performanceis compared with reported multi-standard CMOS LNAs. Notethat the circuit in this paper compares favorably to previousLNAs while showing continuous frequency tuning capability.CONCLUSIONSThe experimental performance of a continuously-tunedCMOS LNA has been presented. The chip has been fabricatedin a 90-nm CMOS technology and uses a single 1V supply1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.30-5-10-15-20-25-30Freq. (GHz)S11(dB)(a)1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5131415161718192021222324Freq. (GHz)S21(dB)(b)Fig. 6. Illustrating the reconfiguration of S-parameters: (a) S11 (b) S21.0.6 0.8 1 1.2 1.4 1.6 2.4 2.61.8 2 2.22.533.544.55Freq. (GHz)NF(dB)1.7 1.8 1.9 2 2.1 2.2242220181614120-5-10-15-20-25-30Freq. (GHz)S11(dB)S21(dB)S11S21-26.1 dB22.82 dB(a)0.6 0.8 1 1.2 1.4 1.6 2.4 2.62.61.8 2 2.234Freq. (GHz)NF(dB)2.83.23.43.63.84.24.44.61.8 1.9 2 2.1 2.2201816140-10Freq. (GHz)S11(dB)S21(dB)S11S212.3-14-12-8-6-4-215171921-12.9 dB20.49 dB(b)Fig. 7. Measured NF and S-parameters for (a) GSM and (b) WCDMA.voltage. The combination of adaptive biasing and PMOS-varactor based tuning networks allows us to adapt the per-formance of the circuit to a number of specifications in a con-tinuous way. Laboratory measurements show a competitive be-havior as compared with the state-of-the art on multi-standardLNAs, whereas keeping a reduced number of inductors —similar to the mono-standard case. To the best of the authors’knowledge, the chip presented in this brief, constitutes oneof the first experimental evidences of real digitally-controlledLNAs, showing a frequency tuning range of approximately500-MHz around a 2GHz operation frequency.REFERENCES[1] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits.United Kingdom: Cambrige University Press, 2 ed., 2004.[2] M. Brandolini, P. Rossi, D. Manstretta, and F. Svelto, “Toward Multi-standard Mobile Terminals - Fully Integrated Receivers Requirementsand Architectures,” IEEE Transactions on Microwave Theory and Tech-niques, vol. 53, pp. 1026–1038, 2005.[3] V. Vidojkovic et al., “Fully-integrated DECT/Bluetooth multi-band LNAin 0.18um CMOS,” IEEE International Symposium on Circuits andSystems, pp. 565–568, 2004.[4] Y. Koolivand, O. Shoaei, A. Zahabi, H. Shamsi, and P. Jabedar-Maralani, “A new technique for design CMOS LNA for multi-standardreceivers,” IEEE International Symposium on Circuits and Systems,vol. 4, pp. 3231–3234, 2005.[5] C.-W. Ang, Y. Zheng, and C.-H. Heng, “A Multi-band CMOS LowNoise Amplifier for Multi-standard Wireless Receivers,” IEEE Interna-tional Symposium on Circuits and Systems, pp. 2802–2805, 2007.[6] P.-I. Mak, S.-P. U, and R. Martins, “Transceiver Architecture Selection:Review, State-of-the-Art Survey and Case Study,” IEEE Circuits andSystems Magazine, 2007.[7] F. Tzeng, A. Jahanian, and P. Heydari, “A Multiband Inductor-ReuseCMOS Low-Noise Amplifier,” IEEE Transactions on Circuits andSystems II: Express Briefs, vol. 55, pp. 209–213, Mar 2008.[8] Z. Li, R. Quintal, and K. O, “A dual-band CMOS front-end with twogain modes for wireless LAN applications,” IEEE Journal of Solid-StateCircuits, vol. 39, pp. 2069–2073, Nov 2004.[9] H. Hashemi and A. Hajimiri, “Concurrent multiband low-noiseamplifiers-theory, design, and applications,” IEEE Transactions on Mi-crowave Theory and Techniques, vol. 50, pp. 288–301, Jan 2002.[10] H. Song, H. Kim, K. Han, J. Choi, C. Park, and B. Kim, “A Sub-2 dBNF Dual-Band CMOS LNA for CDMA/WCDMA Applications,” IEEEMicrowave and Wireless Components Letters, vol. 18, pp. 212–214, Mar2008.[11] S.-W. Kao, M.-C. Kuo, C.-S. Wang, Y.-B. Lee, C.-H. Chen, P.-U. Su,and T.-Y. Yang, “A Low-Power Dual-Band WLAN CMOS Receiver,”Asian Solid-State Circuits Conference, pp. 397–400, 2005.[12] C.-R. Wu and L.-H. Lu, “A 2.9-3.5-GHz tunable low-noise amplifier,”Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems,pp. 206–209, 2006.[13] A. Liscidini, M. Brandolini, D. Sanzogni, and R. Castello, “A 0.13umCMOS front-end, for DCS1800/UMTS/802.11b-g with multiband posi-tive feedback low-noise amplifier,” IEEE Journal of Solid-State Circuits,vol. 41, pp. 981–989, Apr 2006.TABLE ILNA PERFORMANCE AND COMPARISON WITH STATE OF THE ARTRef. Standard IIP3 (dBm) NF (dB) PDC (mW) S21 (dB)[5]GSM 900 -12.8 4.632.418WLAN b/g -15.3 4.43 24WLAN a -14.7 4.42 23[7]WLAN b/g -21.4 3.1 1.0810WLAN a -6.7 3.8 1.02[8]ISM -6.6 2.6 3 22.8UNII -1 6.2 9.1 22.2[9]WLAN b/g 0 2.3414WLAN a 5.6 4.5 15.5[10]CDMA -5.8 1.757.58.42WCDMA -5.3 1.97 10.97[11]WLAN b/g 4 2.8 16 14WLAN a -3 3.9 19 16[12] 2.9GHz–3.5GHz -10 3.6 18 6[13]GSM -7.5 5.22428.5WCDMA 0 5.6 29.5WLAN b/g -4.8 5.8 23.41.78 GHz -9.74 3.62 19.741.84 GHz -10.24 3.65 19.6This 1.92 GHz (GSM) -10.11 3.62 23 22.82Work 1.98 GHz -10.22 3.59 22.312.045 GHz (WCDMA) -10.5 3.43 20.492.1 GHz -10.5 3.48 20.53

Design issues and experimental characterization of a continuously-tuned adaptive CMOS LNA

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Design issues and experimental characterization of a continuously-tuned adaptive CMOS LNA

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