13 research outputs found

    A wideband linear tunable CDTA and its application in field programmable analogue array

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    This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

    High-Speed and Low-Power PID Structures for Embedded Applications.

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    International audienceIn embedded control applications, control-rate and energyconsumption are two critical design issues. This paper presents a series of highspeed and low-power finite-word-length PID controllers based on a new recursive multiplication algorithm. Compared to published results into the same conditions, savings of 431% and 20% are respectively obtained in terms of control-rate and dynamic power consumption. In addition, the new multiplication algorithm generates scalable PID structures that can be tailored to the desired performance and power budget. All PIDs are implemented at RTL level as technology-independent reusable IP-cores. They are reconfigurable according to two compile-time constants: set-point word-length and latency

    Novel Floating General Element Simulators Using CBTA

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    In this study, a novel floating frequency dependent negative resistor (FDNR), floating inductor, floating capacitor and floating resistor simulator circuit employing two CBTAs and three passive components is proposed. The presented circuit can realize floating FDNR, inductor, capacitor or resistor depending on the passive component selection. Since the passive elements are all grounded, this circuit is suitable for fully integrated circuit design. The circuit does not require any component matching conditions, and it has a good sensitivity performance with respect to tracking errors. Moreover, the proposed FDNR, inductance, capacitor and resistor simulator can be tuned electronically by changing the biasing current of the CBTA or can be controlled through the grounded resistor or capacitor. The high-order frequency dependent element simulator circuit is also presented. Depending on the passive component selection, it realizes high-order floating circuit defining as V(s) = snAI(s) or V(s) = s-nBI(s). The proposed floating FDNR simulator circuit and floating high-order frequency dependent element simulator circuit are demonstrated by using PSPICE simulation for 0.25 ÎŒm, level 7, TSMC CMOS technology parameters

    Supplementary Inductance Simulator Topologies Employing Single DXCCII

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    In this study, six grounded inductance simulator circuits are presented including additional useful features in comparison to previous dual-X current conveyor (DXCCII) based implementations. To demonstrate the performance and usefulness of the presented circuits, one of them is used to construct a fifth order Butterworth high-pass filter and a current-mode multifunction filter as application examples. Simulation results are given to confirm the theoretical analysis. The derived DXCCII and its applications are simulated using CMOS 0.35 ÎŒm technology

    Performance analysis of a three-stage quadrature RC generator with operational amplifiers

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    This paper presents the special features of RC harmonic oscillation generators and their widespread use and in particular the quadrature generators which provide two output signals dephased at 90Âș or 270Âș. Quadrature generators can be classified as those with an aperiodic frequency-determining circuit or with a phase inverter group which are used to generate oscillations of one or more fixed frequencies. Studies of a three-stage quadrature RC generator circuit with operational amplifiers have been performed. The results obtained from the simulation and experimental studies performed are presented for the selected circuit. It can be assumed that the experimental and simulation results completely coincide to an accuracy of up to 20% for the amplitude of the generated signals and to the total accuracy for the generated frequency. Quadrature generators are very widely used in communication technology and, most importantly, in the structure of digital frequency, phase and quadrature-amplitude modulators and demodulators, in vector RLC meters and many other electronic circuits and devices in practice

    Low Voltage Low Power Analogue Circuits Design

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    DisertačnĂ­ prĂĄce je zaměƙena na vĂœzkum nejbÄ›ĆŸnějĆĄĂ­ch metod, kterĂ© se vyuĆŸĂ­vajĂ­ pƙi nĂĄvrhu analogovĂœch obvodĆŻ s vyuĆŸitĂ­ nĂ­zkonapěƄovĂœch (LV) a nĂ­zkopƙíkonovĂœch (LP) struktur. Tyto LV LP obvody mohou bĂœt vytvoƙeny dĂ­ky vyspělĂœm technologiĂ­m nebo takĂ© vyuĆŸitĂ­m pokročilĂœch technik nĂĄvrhu. DisertačnĂ­ prĂĄce se zabĂœvĂĄ prĂĄvě pokročilĂœmi technikami nĂĄvrhu, pƙedevĆĄĂ­m pak nekonvenčnĂ­mi. Mezi tyto techniky patƙí vyuĆŸitĂ­ prvkĆŻ s ƙízenĂœm substrĂĄtem (bulk-driven - BD), s plovoucĂ­m hradlem (floating-gate - FG), s kvazi plovoucĂ­m hradlem (quasi-floating-gate - QFG), s ƙízenĂœm substrĂĄtem s plovoucĂ­m hradlem (bulk-driven floating-gate - BD-FG) a s ƙízenĂœm substrĂĄtem s kvazi plovoucĂ­m hradlem (quasi-floating-gate - BD-QFG). PrĂĄce je takĂ© orientovĂĄna na moĆŸnĂ© zpĆŻsoby implementace znĂĄmĂœch a modernĂ­ch aktivnĂ­ch prvkĆŻ pracujĂ­cĂ­ch v napěƄovĂ©m, proudovĂ©m nebo mix-mĂłdu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za Ășčelem potvrzenĂ­ funkčnosti a chovĂĄnĂ­ vĂœĆĄe zmĂ­něnĂœch struktur a prvkĆŻ byly vytvoƙeny pƙíklady aplikacĂ­, kterĂ© simulujĂ­ usměrƈovacĂ­ a induktančnĂ­ vlastnosti diody, dĂĄle pak filtry dolnĂ­ propusti, pĂĄsmovĂ© propusti a takĂ© univerzĂĄlnĂ­ filtry. VĆĄechny aktivnĂ­ prvky a pƙíklady aplikacĂ­ byly ověƙeny pomocĂ­ PSpice simulacĂ­ s vyuĆŸitĂ­m parametrĆŻ technologie 0,18 m TSMC CMOS. Pro ilustraci pƙesnĂ©ho a ĂșčinnĂ©ho chovĂĄnĂ­ struktur je v disertačnĂ­ prĂĄci zahrnuto velkĂ© mnoĆŸstvĂ­ simulačnĂ­ch vĂœsledkĆŻ.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

    New Possibilities In Low-voltage Analog Circuit Design Using Dtmos Transistors

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    (Doktora) -- Ä°stanbul Teknik Üniversitesi, Fen Bilimleri EnstitĂŒsĂŒ, 2013(PhD) -- Ä°stanbul Technical University, Institute of Science and Technology, 2013Bu çalÄ±ĆŸmada DTMOS yaklaĆŸÄ±mı çok dĂŒĆŸĂŒk besleme gerilimlerinde çalÄ±ĆŸan çok dĂŒĆŸĂŒk gĂŒĂ§ tĂŒketimli devrelere baƟarıyla uygulanmÄ±ĆŸtır. Tasarlanan devreler arasında OTA, OP-AMP, CCII gibi analog aktif yapı blokları, çarpma devresi, sadece-MOS yapılar gibi devreler bulunmaktadır. Tasarlanan devreler SPICE benzetimleri ile doğrulanmÄ±ĆŸtır. Ä°leri yönde gövde kutuplamaya bağlı olarak DTMOS transistorun yapısından kaynaklanan, efektif olarak dĂŒĆŸĂŒk eƟik gerilimli çalÄ±ĆŸma özelliği nedeniyle, çok dĂŒĆŸĂŒk gĂŒĂ§ tĂŒketimli ve çok dĂŒĆŸĂŒk gerilimli devrelerde DTMOS yaklaĆŸÄ±mının geçerli bir alternatif olduğu bu çalÄ±ĆŸmayla gösterilmiƟtir. DTMOS yaklaĆŸÄ±mının geniƟ bir alanda çeƟitlilik gösteren analog devre yapılarında çok dĂŒĆŸĂŒk besleme gerilimlerinde bile kabul edilebilir bir performansla kullanılabileceği bulunmuƟtur.In this study, DTMOS approach to the design of ultra low-voltage and ultra low-power analog circuits, has been successfully applied to the circuits ranging from EEG filtering circuits, speech processing filters in hearing aids, multipliers, analog active building blocks: OTA, OP-AMP, CCII to MOS-only circuits. The proposed circuits are verified with SPICE simulations. It is found that in designing ultra low-voltage, ultra low-power analog circuits, DTMOS approach is a viable alternative due to its inherent characteristic of effective low threshold voltage behaviour under forward body bias. This approach can be applied to several analog application subjects with acceptable performance under even ultra low supply voltages.DoktoraPh

    Arbitrarily Tunable Phase Shift in Low-Frequency Multiphase Oscillator

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    A special electronically tunable multiphase oscillator with arbitrarily and continuously adjustable phase shifts is introduced. Our design assumes to set the phase around the asymptotical limit of 180.. These features cannot be easily achieved in a standard way, i.e., any simple single-phase oscillator supplemented by a first-order adjustable all-pass (AP) section (shifter). The proposed design uses an electronically linearly tunable quadrature oscillator with a frequency range from 0.98 up to 12.54 kHz. It also offers multiples of 45. as the initial setting of the phase shift tuning region. The example of operation shows the adjustment of the phase shift at a specific frequency (10 kHz) within the range of +/- 45 degrees. and around -180 degrees, -135 degrees, and -90 degrees. This variability is not available in standard cases without the use of several AP sections. The current value of the phase shift of the presented oscillator is electronically controlled and does not influence the oscillation frequency and condition of oscillation. Output levels of produced signals are not influenced by this tuning process and are in the range of several hundreds of mV. Two applications of the oscillator are proposed. The first one focuses on low-bitrate modulation systems [phase shift keying (PSK)] while in the second one, our circuit represents a source of phase-adjustable signals in acoustic experiments. Discrete passive elements and active devices (special multipliers having current output terminals, unity-gain differential voltage buffers) fabricated in 0.35 mu m I3T25 ON Semiconductor 3.3 V CMOS process are used in experimental verification
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