140 research outputs found

    Buffer Overflow Management with Class Segregation

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    We consider a new model for buffer management of network switches with Quality of Service (QoS) requirements. A stream of packets, each attributed with a value representing its Class of Service (CoS), arrives over time at a network switch and demands a further transmission. The switch is equipped with multiple queues of limited capacities, where each queue stores packets of one value only. The objective is to maximize the total value of the transmitted packets (i.e., the weighted throughput). We analyze a natural greedy algorithm, GREEDY, which sends in each time step a packet with the greatest value. For general packet values (v1<<vm)(v_1 < \cdots < v_m), we show that GREEDY is (1+r)(1+r)-competitive, where r=max1im1{vi/vi+1}r = \max_{1\le i \le m-1} \{v_i/v_{i+1}\}. Furthermore, we show a lower bound of 2vm/i=1mvi2 - v_m / \sum_{i=1}^m v_i on the competitiveness of any deterministic online algorithm. In the special case of two packet values (1 and α>1\alpha > 1), GREEDY is shown to be optimal with a competitive ratio of (α+2)/(α+1)(\alpha + 2)/(\alpha + 1)

    Greedy Algorithms for Multi-Queue Buffer Management with Class Segregation

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    In this paper, we focus on a multi-queue buffer management in which packets of different values are segregated in different queues. Our model consists of m packets values and m queues. Recently, Al-Bawani and Souza (arXiv:1103.6049v2 [cs.DS] 30 Mar 2011) presented an online multi-queue buffer management algorithm Greedy and showed that it is 2-competitive for the general m-valued case, i.e., m packet values are 0 < v_{1} < v_{2} < ... < v_{m}, and (1+v_{1}/v_{2})-competitive for the two-valued case, i.e., two packet values are 0 < v_{1} < v_{2}. For the general m-valued case, let c_i = (v_{i} + \sum_{j=1}^{i-1} 2^{j-1} v_{i-j})/(v_{i+1} + \sum_{j=1}^{i-1}2^{j-1}v_{i-j}) for 1 \leq i \leq m-1, and let c_{m}^{*} = \max_{i} c_{i}. In this paper, we precisely analyze the competitive ratio of Greedy for the general m-valued case, and show that the algorithm Greedy is (1+c_{m}^{*})-competitive.Comment: 19 page

    Quality of Service over Specific Link Layers: state of the art report

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    The Integrated Services concept is proposed as an enhancement to the current Internet architecture, to provide a better Quality of Service (QoS) than that provided by the traditional Best-Effort service. The features of the Integrated Services are explained in this report. To support Integrated Services, certain requirements are posed on the underlying link layer. These requirements are studied by the Integrated Services over Specific Link Layers (ISSLL) IETF working group. The status of this ongoing research is reported in this document. To be more specific, the solutions to provide Integrated Services over ATM, IEEE 802 LAN technologies and low-bitrate links are evaluated in detail. The ISSLL working group has not yet studied the requirements, that are posed on the underlying link layer, when this link layer is wireless. Therefore, this state of the art report is extended with an identification of the requirements that are posed on the underlying wireless link, to provide differentiated Quality of Service

    Towards high quality and flexible future internet architectures

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    Dynamic Traffic Scheduling and Resource Reservation Algorithms for Output-Buffered Switches

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    Scheduling algorithms implemented in Internet switches have been dominated by the best-effort and guaranteed service models. Each of these models encompasses the extreme ends of the correlation spectrum between service guarantees and resource utilisation. Recent advancements in adaptive applications have motivated active research in predictive service models and dynamic resource reservation algorithms. The OCcuPancy_Adjusting (OCP_A) is a scheduling algorithm focused on the design of the above-mentioned research areas. Previously, this algorithm has been analysed for a unified resource reservation and scheduling algorithm while implementing a tail discarding strategy. However, the differentiated services provided by the OCP _A algorithm can be further enhanced. In this dissertation, four new algorithms are proposed. Three are extensions of the OCP _A. The fourth algorithm is an enhanced version of the Virtual Clock (VC) algorithm, denoted as ACcelErated (ACE) scheduler. The first algorithm is a priority scheduling algorithm (i.e. known as the M-Tier algorithm) incorporated with a multitier dynamic resource reservation algorithm. Periodical resource reallocations are implemented. Thus. enabling each tier's resource utilisation to converge to its desired Quality of Service (QoS) operating point. In addition. the algorithm integrates a cross-sharing concept of unused resources between the various hierarchical levels to exemplify the respective QoS sensitivity. In the second algorithm. a control parameter is integrated into the M-Tier algorithm to ensure reduction of delay segregation effects towards packet loss sensitive traffic. The third algorithm, introduces a delay approximation algorithm to justify packet admission. The fourth algorithm enhances the VC scheduling algorithm. This is performed via the incorporation of dynamic features in the computation of the VC scheduling tag. Subsequently, the delay bound limitation of the parameter is eliminated

    Online packet scheduling for CIOQ and buffered crossbar switches

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    We consider the problem of online packet scheduling in Combined Input and Output Queued (CIOQ) and buffered crossbar switches. In the widely used CIOQ switches, packet buffers (queues) are placed at both input and output ports. An N×N CIOQ switch has N input ports and N output ports, where each input port is equipped with N queues, each of which corresponds to an output port, and each output port is equipped with only one queue. In each time slot, arbitrarily many packets may arrive at each input port, and only one packet can be transmitted from each output port. Packets are transferred from the queues of input ports to the queues of output ports through the internal fabric. Buffered crossbar switches follow a similar design, but are equipped with additional buffers in their internal fabric. In either model, our goal is to maximize the number or, in case the packets have weights, the total weight of transmitted packets. Our main objective is to devise online algorithms that are both competitive and efficient. We improve the previously known results for both switch models, both for unweighted and weighted packets. For unweighted packets, Kesselman and Rosén (J. Algorithms 60(1):60–83, 2006) give an online algorithm that is 3-competitive for CIOQ switches. We give a faster, more practical algorithm achieving the same competitive ratio. In the buffered crossbar model, we also show 3-competitiveness, improving the previously known ratio of 4. For weighted packets, we give 5.83- and 14.83-competitive algorithms with an elegant analysis for CIOQ and buffered crossbar switches, respectively. This improves upon the previously known ratios of 6 and 16.24

    Node design in optical packet switched networks

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    On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

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    For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices
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