An audio FIR-DAC in a BCD process for high power Class-D amplifiers

A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at V/sub dd/ = 5 V and the chip area is 2 mm/sup 2/ including the reference diode that can be shared by more channels

Bipolar-CMOS-DMOS Process-Based a Robust and High-Accuracy Low Drop-Out Regulator

A 40V BCD process high-accuracy and robust Low Drop-Out Regulator was proposed and tape-out in CSMC; the LDO was integrated in a LED Control and Driver SOC of outdoor applications. The proposed LDO converted the 12V~40V input power to 5V for the low voltage circuits inside the SOC. The robustness of LDO was important because the application condition of the SOC was bad. It was simulated in all process corner, -55℃~150℃ temperature and 12V~40V power voltage conditions. Simulation result shows that the LDO works robustly in conditions mentioned above. The default precision of LDO output voltage is ±2.75% max in all conditions, moreover, by utilizing a trim circuit in the feedback network, the precision can be improved to ±0.5% max after being trimmed by 3 bit digital trim signal Trim[3:1]. The total size of the proposed LDO is 135um*450um and the maximum current consumption is 284uA

A breakdown voltage model for implanted resurf p-LDMOS device on n+ buried layer

This paper presents an analytical expression of the breakdown voltage of a high voltage implanted RESURF p-LDMOS device which uses the n+ buried layer as an effective device substrate. In this model, the doping profile of the buried layer is considered and discussed. The implant dose for the drift region to implement the RESURF principle is also described by this model. Results calculated from this model are verified by experimental values

A High-Efficiency 4x45W Car Audio Power Amplifier using Load Current Sharing

A 4x45W (EIAJ) monolithic car audio power amplifier is presented that achieves a power dissipation decrease of nearly 2x over standard class AB operation by sharing load currents between loudspeakers. Output signals are conditioned using a common-mode control loop to allow switch placement between loads with minimal THD increase. A prototype is realized in a SOI bipolar-CMOS-DMOS process with 0.5μm feature size. Die area is 7.5x4.6mm2. THD+N @(1kHz,10W) is 0.05%

Time interleaved optical sampling for ultra-high speed A/D conversion

A scheme is proposed for increasing the sampling rate of analogue-to-digital conversion by more than an order of magnitude by combining state-of-the-art A/D converters with photonic technology. Ultra-high speed sampling is performed optically by a multiwavelength pulse train. Wavelength demultiplexers convert the high repetition rate data stream of samples into parallel data streams that can be handled by available electronic A/D converters

Transconductor and integrator circuits for integrated bipolar video frequency filters

A description is presented of novel transconductor and integrator circuits which can be used in integrated video frequency filters in bipolar technology. The transconductor consists of a parallel connection of a passive nominal transconductance and an active variable transconductance, resulting in good high-frequency performance up to 70 MHz and less than 1% linearity error for input signals up to 2V pp. The integrator incorporates an operation transconductance amplifier circuit which provides a tunable integrator phase. Simulation results for all circuits and for a fifth-order elliptic low-pass filter with a nominal cutoff frequency of 5 MHz are presente

Front-end Electronics for Silicon Trackers readout in Deep Sub-Micron CMOS Technology: The case of Silicon strips at the ILC

For the years to come, Silicon strips detectors will be read using the smallest available integrated technologies for room, transparency, and power considerations. CMOS, Bipolar- CMOS and Silicon-Germanium are presently offered in deepsubmicron (250 down to 90nm) at affordable cost through worldwide integrated circuits multiproject centers. As an example, a 180nm CMOS readout prototype chip has been designed and tested, and gave satisfactory results in terms of noise and power. Beam tests are under work, and prospectives in 130nm will be presented

A wireless implantable multichannel digital neural recording system for a micromachined sieve electrode

This paper reports the development of an implantable, fully integrated, multichannel peripheral neural recording system, which is powered and controlled using an RF telemetry link, The system allows recording of +/-500 mu V neural signals from axons regenerated through a micromachined silicon sieve electrode, These signals are amplified using on-chip 100 Hz to 3.1 kHz bandlimited amplifiers, multiplexed, and digitized with a low-power (<2 mW), moderate speed (8 mu s/b) current-mode 8-b analog-to-digital converter (ADC), The digitized signal is transmitted to the outside world using a passive RF telemetry link, The circuit is implemented using a bipolar CMOS process, The signal processing CMOS circuitry dissipates only 10 mW of power from a 5-V supply while operating at 2 MHz and consumes 4 x 4 mm(2) of area, The overall circuit including the RF interface circuitry contains over 5000 transistors, dissipates 90 mW of power, and consumes 4 x 6 mm(2) of area

The characterization of recycled concrete aggregate as filter in removal of phosphorus

Phosphorus (P) is one of the key nutrients that lead to eutrophication problem in surface water. However, the existing conventional wastewater treatment system to remove phosphorus is expensive and require a complex process. Therefore, a system using low cost and environmental friendly should be practiced to overcome this problem. Recycled concrete aggregate (RCA) used as a filter system emerged as an alternative technology for phosphorus removal. This can overcome the problem of construction site waste by converting the waste into something valuable products. Thus, this study aim to investigate the physical and chemical characteristic of RCA that influenced adsorption of P. RCA was analyzed using Scanning Electron Microscopy (SEM) and Energy-dispersive X-ray spectroscopy (EDX) testing to determine chemical composition. Results shows that RCA is highly contained with Aluminium, Calcium and Magnesium elements that enhanced the Phosphorus adsorption