Improved Accuracy Area Efficient Hybrid CMOS/GaN DC-DC Buck Converterfor High Step-Down Ratio Applications

abstract: Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Dynamic modeling of pwm and single-switch single-stage power factor correction converters

The concept of averaging has been used extensively in the modeling of power electronic circuits to overcome their inherent time-variant nature. Among various methods, the PWM switch modeling approach is most widely accepted in the study of closed-loop stability and transient response because of its accuracy and simplicity. However, a non-ideal PWM switch model considering conduction losses is not available except for converters operating in continuous conduction mode (CCM) and under small ripple conditions. Modeling of conductor losses under large ripple conditions has not been reported in the open literature, especially when the converter operates in discontinuous conduction mode (DCM). In this dissertation, new models are developed to include conduction losses in the non-ideal PWM switch model under CCM and DCM conditions. The developed model is verified through two converter examples and the effect of conduction losses on the steady state and dynamic responses of the converter is also studied. Another major constraint of the PWM switch modeling approach is that it heavily relies on finding the three-terminal PWM switch. This requirement severely limits its application in modeling single-switch single-stage power factor correction (PFC) converters, where more complex topological structures and switching actions are often encountered. In this work, we developed a new modeling approach which extends the PWM switch concept by identifying the charging and discharging voltages applied to the inductors. The new method can be easily applied to derive large-signal models for a large group of PFC converters and the procedure is elaborated through a specific example. Finally, analytical results regarding harmonic contents and power factors of various PWM converters in PFC applications are also presented here

Modeling and Analysis of Power Processing Systems (MAPPS), initial phase 2

The overall objective of the program is to provide the engineering tools to reduce the analysis, design, and development effort, and thus the cost, in achieving the required performances for switching regulators and dc-dc converter systems. The program was both tutorial and application oriented. Various analytical methods were described in detail and supplemented with examples, and those with standardization appeals were reduced into computer-based subprograms. Major program efforts included those concerning small and large signal control-dependent performance analysis and simulation, control circuit design, power circuit design and optimization, system configuration study, and system performance simulation. Techniques including discrete time domain, conventional frequency domain, Lagrange multiplier, nonlinear programming, and control design synthesis were employed in these efforts. To enhance interactive conversation between the modeling and analysis subprograms and the user, a working prototype of the Data Management Program was also developed to facilitate expansion as future subprogram capabilities increase

ASDTIC control and standardized interface circuits applied to buck, parallel and buck-boost dc to dc power converters

Versatile standardized pulse modulation nondissipatively regulated control signal processing circuits were applied to three most commonly used dc to dc power converter configurations: (1) the series switching buck-regulator, (2) the pulse modulated parallel inverter, and (3) the buck-boost converter. The unique control concept and the commonality of control functions for all switching regulators have resulted in improved static and dynamic performance and control circuit standardization. New power-circuit technology was also applied to enhance reliability and to achieve optimum weight and efficiency

Single-Phase Bi-directional Ćuk Inverter for Battery Applications

Bidirectional inverters are widely applied in photovoltaic and wind systems that require battery power backup. They are advantageous over unidirectional inverters because of their ability to convert DC power into AC power and then AC power back into DC power to recharge for storage purposes. Generally, bidirectional inverters are designed to have multiple power stages and/or make use of transformers for isolation and voltage/current gain. This usually increases the cost of production and oftentimes reduces the efficiency of the system. At the same time, attempts at eliminating usage of transformers and reduction in the number of power stages limits the range of bidirectional inverters’ capabilities. This is because battery applications today require low voltage DC-AC inverters with AC-DC power flow capability to store energy for later use. As such, only buck-boost based topologies are majorly being proposed and used for this functionality. The buck boost converter is the most widely used in such applications because of its higher efficiency, low component count and simple structure. It has drawbacks, however, such as: pulsating input and output currents - this leads to lower high electromagnetic interference; lower power factor during AC-DC power flow rectification when the batteries are being recharged; and external filter is also required during this power flow to keep the charging voltage constant. This research proposes a bidirectional inverter that attempts to overcome the drawbacks of the widely used buck-boost converter-based topology. The bidirectional inverter proposed in this work is based on a bidirectional Ćuk converter. The Ćuk converter has both continuous input and output currents. A galvanic isolation option on a Ćuk converter is simpler than a buck boost converter - this is important for grid tied systems. The inverter is based on a pseudo DC-link architecture - it uses a front end Ćuk converter cascaded with an unfolding bridge to convert DC power into AC power. The switches in the converter stage are switched at high frequency, while the switches in the unfolding stage are switched slower at the grid frequency. This configuration is desirable over the two-stage topologies because the switching losses in the unfolding bridge are lower because of this low switching frequency used. This configuration also ensures good switch utilization at the unfolding stage by lowering the parasitic effects on the power transfer. The proposed inverter has 4 modes of operation: during modes I and II the power is positive, and it converts DC power into AC power; during modes III and IV the power is negative, and it converts AC power back into DC power. The inverter is designed such that during DC-AC power flow, the input and output inductor currents and coupling capacitor voltage are continuous for improved efficiency. During the AC-DC power flow, the coupling capacitor voltage is discontinuous to achieve a higher input power factor by improving the AC line current, thereby simultaneously increasing the efficiency. The inverter was analysed in terms of: the dead time inserted into the switches to avoid shoot through and shortcircuiting switches; the parasitic effects on the power transfer ratio. Because the Cúk inverter is a high order system, several robust control strategies, such as sliding mode and current control have been proposed. These control methods require complex theory and present practical challenges to be reviewed. As such a new nested loop control strategy was proposed based on the dynamics of the coupling capacitor as the primary energy storage in the Cúk inverter. The control strategy uses 2 loops: an inner current loop and an outer voltage loop. Lead compensators were designed for both the current and voltage loops to achieve good dynamic response at a high bandwidth. Both simulated and experimental results showed that the bidirectional inverter was able to meet the design specifications. The control strategy showed good dynamic response and disturbance rejection under several inverter variations. Although the efficiency during simulations was above 96%, the experimental efficiency dropped significantly because the inverter was built on a Vero board for easy manipulation. The AC input power factor was > 0.95 for both simulated and experimental results

An enhanced model for small-signal analysis of the phase-shifted full-bridge converter

This paper presents an in-depth critical discussion and derivation of a detailed small-signal analysis of the Phase-Shifted Full-Bridge (PSFB) converter. Circuit parasitics, resonant inductance and transformer turns ratio have all been taken into account in the evaluation of this topology’s open-loop control-to-output, line-to-output and load-to-output transfer functions. Accordingly, the significant impact of losses and resonant inductance on the converter’s transfer functions is highlighted. The enhanced dynamic model proposed in this paper enables the correct design of the converter compensator, including the effect of parasitics on the dynamic behavior of the PSFB converter. Detailed experimental results for a real-life 36V-to-14V/10A PSFB industrial application show excellent agreement with the predictions from the model proposed herein.

Modeling and Analysis of Power Processing Systems (MAPPS). Volume 1: Technical report

Computer aided design and analysis techniques were applied to power processing equipment. Topics covered include: (1) discrete time domain analysis of switching regulators for performance analysis; (2) design optimization of power converters using augmented Lagrangian penalty function technique; (3) investigation of current-injected multiloop controlled switching regulators; and (4) application of optimization for Navy VSTOL energy power system. The generation of the mathematical models and the development and application of computer aided design techniques to solve the different mathematical models are discussed. Recommendations are made for future work that would enhance the application of the computer aided design techniques for power processing systems

Electrical performance characteristics of high power converters for space power applications

The first goal of this project was to investigate various converters that would be suitable for processing electric power derived from a nuclear reactor. The implementation is indicated of a 20 kHz system that includes a source converter, a ballast converter, and a fixed frequency converter for generating the 20 kHz output. This system can be converted to dc simply by removing the fixed frequency converter. This present study emphasized the design and testing of the source and ballast converters. A push-pull current-fed (PPCF) design was selected for the source converter, and a 2.7 kW version of this was implemented using three 900 watt modules in parallel. The characteristic equation for two converters in parallel was derived, but this analysis did not yield any experimental methods for measuring relative stability. The three source modules were first tested individually and then in parallel as a 2.7 kW system. All tests proved to be satisfactory; the system was stable; efficiency and regulation were acceptable; and the system was fault tolerant. The design of a ballast-load converter, which was operated as a shunt regulator, was investigated. The proposed power circuit is suitable for use with BJTs because proportional base drive is easily implemented. A control circuit which minimizes switching frequency ripple and automatically bypasses a faulty shunt section was developed. A nonlinear state-space-averaged model of the shunt regulator was developed and shown to produce an accurate incremental (small-signal) dynamic model, even though the usual state-space-averaging assumptions were not met. The nonlinear model was also shown to be useful for large-signal dynamic simulation using PSpice

Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed