Auxiliary-Path-Assisted Digital Linearization of Wideband Wireless Receivers

Wireless communication systems in recent years have aimed at increasing data rates by ensuring flexible and efficient use of the radio spectrum. The dernier cri in this field has been in the area of carrier aggregation and cognitive radio. Carrier aggregation is a major component of LTE-Advanced. With carrier aggregation, a number of separate LTE carriers can be combined, by mobile network operators, to increase peak data rates and overall network capacity. Cognitive radios, on the other hand, allow efficient spectrum usage by locating and using spatially vacant spectral bands. High monolithic integration in these application fields can be achieved by employing receiver architectures such as the wideband direct conversion receiver topology. This is advantageous from the view point of cost, power consumption and size. However, many challenges exist, of particular importance is nonlinear distortion arising from analog front-end components such as low noise amplifiers (LNA). Nonlinear distortions especially become severe when several signals of varying amplitudes are received simultaneously. In such cases, nonlinear distortions stemming from strong signals may deteriorate the reception of the weaker signals, and also impair the receiver’s spectrum sensing capabilities. Nonlinearity, usually a consequence of dynamic range limitation, degrades performance in wideband multi-operator communications systems, and it will have a notable role in future wireless communication system design. This thesis presents a digital domain linearization technique that employs a very nonlinear auxiliary receiver path for nonlinear distortion cancellation. The proposed linearization technique relies on one-time adaptively-determined linearization coefficients for cancelling nonlinear distortions. Specifically, we take a look at canceling the troublesome in-band third order intermodulation products using the proposed technique. The proposed technique can be extended to cancel out both even and higher order odd intermodulation products. Dynamic behavioral models are used to account for RF nonlinearities, including memory effects which cannot be ignored in the wideband scenario. Since the proposed linearization technique involves the use of two receiver paths, techniques for correcting phase delays between the two paths are also introduced. Simplicity is the hallmark of the proposed linearization technique. It can achieve up to +30 dBm in IIP3 performance with ADC resolution being a major performance bottleneck. It also shows strong tolerance to strong blocker nonlinearities

A Comparative Analysis of the Complexity/Accuracy Tradeoff in Power Amplifier Behavioral Models

A comparative study of state-of-the-art behavioral models for microwave power amplifiers (PAs) is presented in this paper. After establishing a proper definition for accuracy and complexity for PA behavioral models, a short description on various behavioral models is presented. The main focus of this paper is on the modeling accuracy as a function of computational complexity. Data is collected from measurements on two PAs—a general-purpose amplifier and a Doherty PA designed for WiMAX—for different output power levels. The models are characterized in terms of accuracy and complexity for both in-band and out-of-band error. The results show that, among the models studied, the generalized memory polynomial behavioral model has the best tradeoff for accuracy versus complexity for both PAs, and can obtain high performance at half of the computational cost of all other models analyzed

Digital Pre-distortion for Interference Reduction in Dynamic Spectrum Access Networks

Given the ever increasing reliance of today’s society on ubiquitous wireless access, the paradigm of dynamic spectrum access (DSA) as been proposed and implemented for utilizing the limited wireless spectrum more efficiently. Orthogonal frequency division multiplexing (OFDM) is growing in popularity for adoption into wireless services employing DSA frame- work, due to its high bandwidth efficiency and resiliency to multipath fading. While these advantages have been proven for many wireless applications, including LTE-Advanced and numerous IEEE wireless standards, one potential drawback of OFDM or its non-contiguous variant, NC-OFDM, is that it exhibits high peak-to-average power ratios (PAPR), which can induce in-band and out-of-band (OOB) distortions when the peaks of the waveform enter the compression region of the transmitter power amplifier (PA). Such OOB emissions can interfere with existing neighboring transmissions, and thereby severely deteriorate the reliability of the DSA network. A performance-enhancing digital pre-distortion (DPD) technique compensating for PA and in-phase/quadrature (I/Q) modulator distortions is proposed in this dissertation. Al- though substantial research efforts into designing DPD schemes have already been presented in the open literature, there still exists numerous opportunities to further improve upon the performance of OOB suppression for NC-OFDM transmission in the presence of RF front-end impairments. A set of orthogonal polynomial basis functions is proposed in this dissertation together with a simplified joint DPD structure. A performance analysis is presented to show that the OOB emissions is reduced to approximately 50 dBc with proposed algorithms employed during NC-OFDM transmission. Furthermore, a novel and intuitive DPD solution that can minimize the power regrowth at any pre-specified frequency in the spurious domain is proposed in this dissertation. Conventional DPD methods have been proven to be able to effectively reduce the OOB emissions that fall on top of adjacent channels. However more spectral emissions in more distant frequency ranges are generated by employing such DPD solutions, which are potentially in violation of the spurious emission limit. At the same time, the emissions in adjacent channel must be kept under the OOB limit. To the best of the author’s knowledge, there has not been extensive research conducted on this topic. Mathematical derivation procedures of the proposed algorithm are provided for both memoryless nonlinear model and memory-based nonlinear model. Simulation results show that the proposed method is able to provide a good balance of OOB emissions and emissions in the far out spurious domain, by reducing the spurious emissions by 4-5 dB while maintaining the adjacent channel leakage ratio (ACLR) improvement by at least 10 dB, comparing to the PA output spectrum without any DPD

ULTRA-WIDEBAND NONLINEAR ECHO-CANCELLATION

Hybrid fiber coaxial (HFC) networks are used around the world to distribute cable television and broadband internet services to customers. These networks are governed by the Data-Over-Cable Service Interface Specification (DOCSIS) family of standards, with the most recent version at the time of this writing being DOCSIS 3.1. A frequency division duplex (FDD) spectrum is used in DOCSIS 3.1, where the upstream and downstream signals are separated in frequency to eliminate interference. A possible method to increase signal bandwidths is to use a full-duplex (FDX) spectrum, in which the US and DS signals use the same frequencies at the same time. A main challenge faced when implementing FDX in a DOCSIS node is eliminating the interference in the received US signal caused by the transmitted DS signal. One possible method for eliminating the interference is utilizing an echo-canceling algorithm, which predicts the self-interference (SI) based on the known DS signal and cancels it from the received US signal. Although echo-cancellation algorithms exist for fundamentally similar applications, the DOCSIS FDX case is more complicated for two main reasons. First, the DOCSIS node uses a nonlinear power amplifier to amplify the DS signal. Second, the DS signal is an ultra-wideband signal spanning a frequency range of up to 1.2 GHz. Most of the amplifier modeling techniques discussed in the literature were designed for narrowband wireless signals and will have limited performance when used with ultra-wideband signals. This thesis develops an algorithm to characterize the power amplifier and to predict the harmonics it generates for a given DS signal. These predicted harmonics can be used to cancel the SI signal in a full duplex DOCSIS system. The algorithm, which is referred to as the ultra-wideband memory polynomial (UWB-MP) model, is based on the well-known memory polynomial model with adaptations which allow the model to predict harmonics for ultra-wideband signals. Since a direct implementation of the UWB-MP model in an FPGA would result in very high resource usage, system architecture recommendations are provided. Our proposed implementation of the model compensates for harmonics up to and including the 3rd order, which has a power spectrum extending above 3600 MHz. Using the techniques discussed in this thesis, it is shown that a sampling rate of 4 GHz allows for cancellation of the SI signal while providing a reasonable balance between performance and resource usage. Matlab simulations of a DOCSIS node with various parameters and PA simulation models were conducted. The simulations showed that over 75 dB of cancellation of the SI signal is possible in an idealized hardware setup. It is also demonstrated that AWGN injected into the received signal does not reduce the ability of the model to estimate the PA harmonics, although the noise itself cannot be canceled. Further simulations showed that the UWB-MP model could cancel harmonics whose power is much higher than that specified in DOCSIS. Although the UWB-MP model was designed with memory polynomial type PAs in mind, simulation results show that significant cancellation is possible with PAs that are represented by Wiener models as well. Based on the simulation results, we recommend using a filter of length 20 coefficients for each harmonic in the UWB-MP model, and 60 iterations with 500 samples for estimating the coefficients with the least squares method

Multi Look-Up Table Digital Predistortion for RF Power Amplifier Linearization

Premi extraordinari doctorat curs 2007-2008, àmbit d’Enginyeria de les TICAquesta Tesi Doctoral se centra en el disseny d'un nou linealitzador de Predistorsió Digital (Digital Predistortion - DPD) capaç de compensar la dinàmica i els efectes no lineals introduïts pels Amplificadors de Potència (Power Amplifiers - PAs). Un dels trets més rellevants d'aquest nou predistorsionador digital i adaptatiu consisteix en ser deduïble a partir d'un model de PA anomenat Nonlinear Auto-Regressive Moving Average (NARMA). A més, la seva arquitectura multi-LUT (multi-Taula) permet la implementació en un dispositiu Field Programmable Gate Array (FPGA).La funció de predistorsió es realitza en banda base, per tant, és independent de la banda freqüencial on es durà a terme l'amplificació del senyal de RF, el que pot resultar útil si tenim en compte escenaris multibanda o reconfigurables. D'altra banda, el fet que aquest DPD tingui en compte els efectes de memòria introduïts pel PA, representa una clara millora de les prestacions aconseguides per un simple DPD sense memòria. En comparació amb d'altres DPDs basats en models més computacionalment complexos, com és el cas de les xarxes neuronals amb memòria (Time-Delayed Neural Networks - TDNN), la estructura recursiva del DPD proposat permet reduir el nombre de LUTs necessàries per compensar els efectes de memòria del PA. A més, la seva estructura multi-LUT permet l'escalabilitat, és a dir, activar or desactivar les LUTs que formen el DPD en funció de la dinàmica que presenti el PA.En una primera aproximació al disseny del DPD, és necessari identificar el model NARMA del PA. Un dels majors avantatges que presenta el model NARMA és la seva capacitat per trobar un compromís entre la fidelitat en l'estimació del PA i la complexitat computacional introduïda. Per reforçar aquest compromís, l' ús d'algoritmes heurístics de cerca, com són el Simulated Annealing o els Genetic Algorithms, s'utilitzen per trobar els retards que millor caracteritzen la memòria del PA i per tant, permeten la reducció del nombre de coeficients necessaris per caracteritzar-la. Tot i així, la naturalesa recursiva del model NARMA comporta que, de cara a garantir l'estabilitat final del DPD, cal dur a terme un estudi previ sobre l'estabilitat del model.Una vegada s'ha obtingut el model NARMA del PA i s'ha verificat l'estabilitat d'aquest, es procedeix a l'obtenció de la funció de predistorsió a través del mètode d'identificació predictiu. Aquest mètode es basa en la continua identificació del model NARMA del PA i posteriorment, a partir del model obtingut, es força al PA perquè es comporti de manera lineal. Per poder implementar la funció de predistorsió en la FPGA, cal primer expressar-la en forma de combinacions en paral·lel i cascada de les anomenades Cel·les Bàsiques de Predistorsió (BPCs), que són les unitats fonamentals que composen el DPD. Una BPC està formada per un multiplicador complex, un port RAM dual que actua com a LUT (taula de registres) i un calculador d'adreces. Les LUTs s'omplen tenint en compte una distribució uniforme dels continguts i l'indexat d'aquestes es duu a terme mitjançant el mòdul de l'envoltant del senyal. Finalment, l'adaptació del DPD consisteix en monitoritzar els senyals d'entrada i sortida del PA i anar duent a terme actualitzacions periòdiques del contingut de les LUTs que formen les BPCs. El procés d'adaptació del contingut de les LUTs es pot dur a terme en la mateixa FPGA encarregada de fer la funció de predistorsió, o de manera alternativa, pot ser duta a terme per un dispositiu extern (com per exemple un DSP - Digital Signal Processor) en una escala de temps més relaxada. Per validar l'exposició teòrica i provar el bon funcionalment del DPD proposat en aquesta Tesi, es proporcionen resultats tant de simulació com experimentals que reflecteixen els objectius assolits en la linealització del PA. A més, certes qüestions derivades de la implementació pràctica, tals com el consum de potència o la eficiència del PA, són també tractades amb detall.This Ph.D. thesis addresses the design of a new Digital Predistortion (DPD) linearizer capable to compensate the unwanted nonlinear and dynamic behavior of power amplifiers (PAs). The distinctive characteristic of this new adaptive DPD is its deduction from a Nonlinear Auto Regressive Moving Average (NARMA) PA behavioral model and its particular multi look-up table (LUT) architecture that allows its implementation in a Field Programmable Gate Array (FPGA) device.The DPD linearizer presented in this thesis operates at baseband, thus becoming independent on the final RF frequency band and making it suitable for multiband or reconfigurable scenarios. Moreover, the proposed DPD takes into account PA memory effects compensation which representsan step forward in overcoming classical limitations of memoryless predistorters. Compared to more computational complex DPDs with dynamic compensation, such Time-Delayed Neural Networks (TDNN), this new DPD takes advantage of the recursive nature of the NARMA structure to relax the number of LUTs required to compensate memory effects in PAs. Furthermore, its parallel multi-LUT architecture is scalable, that is, permits enabling or disabling the contribution of specific LUTs depending on the dynamics presented by a particular PA.In a first approach, it is necessary to identify a NARMA PA behavioral model. The extraction of PA behavioral models for DPD linearization purposes is carried out by means of input and output complex envelope signal observations. One of the major advantages of the NARMA structure regards its capacity to deal with the existing trade-off between computational complexity and accuracy in PA behavioral modeling. To reinforce this compromise, heuristic search algorithms such the Simulated Annealing or Genetic Algorithms are utilized to find the best sparse delays that permit accurately reproducing the PA nonlinear dynamic behavior. However, due to the recursive nature of the NARMA model, an stability test becomes a previous requisite before advancing towards DPD linearization.Once the PA model is identified and its stability verified, the DPD function is extracted applying a predictive predistortion method. This identification method relies just on the PA NARMA model and consists in adaptively forcing the PA to behave as a linear device. Focusing in the DPD implementation, it is possible to map the predistortion function in a FPGA, but to fulfill this objective it is first necessary to express the predistortion function as a combined set of LUTs.In order to store the DPD function into a FPGA, it has to be stated in terms of parallel and cascade Basic Predistortion Cells (BPCs), which are the fundamental building blocks of the NARMA based DPD. A BPC is formed by a complex multiplier, a dual port RAM memory block acting as LUT and an address calculator. The LUT contents are filled following an uniform spacing procedure and its indexing is performed with the amplitude (modulus) of the signal's envelope.Finally, the DPD adaptation consists in monitoring the input-output data and performing frequent updates of the LUT contents that conform the BPCs. This adaptation process can be carried out in the same FPGA in charge of performing the DPD function, or alternatively can be performed by an external device (i.e. a DSP device) in a different time-scale than real-time operation.To support all the theoretical design and to prove the linearization performance achieved by this new DPD, simulation and experimental results are provided. Moreover, some issues derived from practical experimentation, such as power consumption and efficiency, are also reported and discussed within this thesis.Award-winningPostprint (published version

Transmitter Linearization for mm-Wave Communications Systems

There is an ever increasing need for enabling higher data rates in modern communication systems which brings new challenges in terms of the power consumption and nonlinearity of hardware components. These problems become prominent in power amplifiers (PAs) and can significantly degrade the performance of transmitters, and hence the overall communication system. Hence, it is of central importance to design efficient PAs with a linear operation region. This thesis proposes a methodology and a comprehensive framework to address this challenge. This is accomplished by application of predistortion to a mm-wave PA and an E-band IQ transmitter while investigating the trade-offs between linearity, efficiency and predistorter complexity using the proposed framework.In the first line of work, we have focused on a mm-wave PA. A PA has high efficiency at high input power at the expense of linearity, whereas it operates linearly for lower input power levels while sacrificing efficiency. To attain both linearity and efficiency, predistortion is often used to compensate for the PA nonlinearity. Yet, the trade-offs related to predistortion complexities are not fully understood. To address this challenge, we have used our proposed framework for evaluation of predistorters using modulated test signals and implemented it using digital predistortion and a mm-wave PA. This set-up enabled us to investigate the trade-offs between linearity, efficiency and predistorter complexity in a systematic manner. We have shown that to achieve similar linearity levels for different PA classes, predistorters with different complexities are needed and provided guidelines on the achievable limits in term linearity for a given predistorter complexity for different PA classes.In the second line of work, we have focused on linearization of an E-band transmitter using a baseband analog predistorter (APD) and under constraints given by a spectrum emission standard. In order to use the above proposed framework with these components, characterizations of the E-band transmitter and the APD are performed. In contrast to typical approaches in the literature, here joint mitigation of the PA and I/Q modulator impairments is used to model the transmitter. Using the developed models, optimal model parameters in terms of output power at the mask limit are determined. Using these as a starting point, we have iteratively optimized operating point of the APD and linearized the E-band transmitter. The experiments demonstrated that the analog predistorter can successfully increase the output power by 35% (1.3 dB) improvement while satisfying the spectrum emission mask

Multicarrier communication systems with low sensibility to nonlinear amplification

Actualment estem entrant a una nova era de la informació amb gran demanda de sistemes de comunicació sense fils. Nous serveis com dades i video requereixen transmissions fiables d'alta velocitat, fins i tot en escenaris d'alta mobilitat. A més a més, la dificultat d'assignar el limitat espectre radioelèctric juntament amb la necessitat d'incrementar el temps de vida de les bateries dels terminals mòbils, requereix el diseny de transceptors que usin la potència i l'ampla de banda disponibles de manera eficient. Les comunicacions multiportadora basades en OFDM són capaces de satisfer la majoria d'aquests requeriments. Però, entre altres reptes, reduir la sensibilitat a la amplificació no-lineal és un factor clau durant el diseny. En aquesta tesi doctoral s'analitza la sensibilitat dels sistemes multiportadora basats en OFDM a l'amplificació no-lineal i es consideren formes eficients per superar aquest problema. La tesi s'enfoca principalment al problema de reduir les fluctuacions de l'envolupant del senyal transmès. En aquest sentit es presenta també un estudi de les mètriques de l'envolupant del senyal, PAPR i CM. A més a més, basant-nos en l'anàlisis presentat es proposen noves tècniques per sistemes OFDM i MC-SS. Per MC-SS, també es tracta el diseny d'una tècnica de postprocessament en forma de detector multiusuari per canals no-lineals.Actualmente estamos entrando en una nueva era de la información donde se da una gran demanda de sistemas de comunicación inalámbricos. Nuevos servicios como datos y vídeo requieren transmisiones fiables de alta velocidad, incluso en escenarios de alta movilidad. Además, la dificultad de asignar el limitado espectro radioeléctrico junto con la necesidad de incrementar el tiempo de vida de las baterías de los terminales móviles, requiere el diseño de transceptores que usen eficientemente la potencia y el ancho de banda disponibles. Las comunicaciones multiportadora basadas en OFDM son capaces de satisfacer la mayoría de dichos requerimientos. Sin embargo, entre otros retos, reducir su sensibilidad a la amplificación no-lineal es un factor clave durante el diseño. En esta tesis se analiza la sensibilidad de los sistemas multiportadora basados en OFDM a la amplificación no-lineal y se consideran formas eficientes para superar dicho problema. La tesis se enfoca principalmente al problema de reducir las fluctuaciones de la envolvente. En este sentido también se presenta un estudio de las métricas de la señal, PAPR y CM. Además, basándonos en el análisis presentado se proponen nuevas técnicas para OFDM y MC-SS. Para MC-SS, también se trata el diseño de un detector multiusuario para canales no-lineales.We are now facing a new information age with high demand of wireless communication systems. New services such as data and video require achieving reliable high-speed transmissions even in high mobility scenarios. Moreover, the difficulty to allocate so many wireless communication systems in the limited frequency band in addition to the demand for long battery life requires designing spectrum and power efficient transceivers. Multicarrier communications based on OFDM are known to fulfill most of the requirements of such systems. However, among other challenges, reducing the sensitivity to nonlinear amplification has become a design key. In this thesis the sensitivity of OFDM-based multicarrier systems to nonlinear amplification is analyzed and efficient ways to overcome this problem are considered. The focus is mainly on the problem of reducing the envelope fluctuations. Therefore, a study of the signal metrics, namely PAPR and CM, is also presented. From the presented analysis, several new techniques for OFDM and MC-SS are proposed. For MC-SS, the design of a post-processing technique in the form of a multiuser detector for nonlinearly distorted MC-SS symbols is also addressed

Nonlinear models and algorithms for RF systems digital calibration

Focusing on the receiving side of a communication system, the current trend in pushing the digital domain ever more closer to the antenna sets heavy constraints on the accuracy and linearity of the analog front-end and the conversion devices. Moreover, mixed-signal implementations of Systems-on-Chip using nanoscale CMOS processes result in an overall poorer analog performance and a reduced yield. To cope with the impairments of the low performance analog section in this "dirty RF" scenario, two solutions exist: designing more complex analog processing architectures or to identify the errors and correct them in the digital domain using DSP algorithms. In the latter, constraints in the analog circuits' precision can be offloaded to a digital signal processor. This thesis aims at the development of a methodology for the analysis, the modeling and the compensation of the analog impairments arising in different stages of a receiving chain using digital calibration techniques. Both single and multiple channel architectures are addressed exploiting the capability of the calibration algorithm to homogenize all the channels' responses of a multi-channel system in addition to the compensation of nonlinearities in each response. The systems targeted for the application of digital post compensation are a pipeline ADC, a digital-IF sub-sampling receiver and a 4-channel TI-ADC. The research focuses on post distortion methods using nonlinear dynamic models to approximate the post-inverse of the nonlinear system and to correct the distortions arising from static and dynamic errors. Volterra model is used due to its general approximation capabilities for the compensation of nonlinear systems with memory. Digital calibration is applied to a Sample and Hold and to a pipeline ADC simulated in the 45nm process, demonstrating high linearity improvement even with incomplete settling errors enabling the use of faster clock speeds. An extended model based on the baseband Volterra series is proposed and applied to the compensation of a digital-IF sub-sampling receiver. This architecture envisages frequency selectivity carried out at IF by an active band-pass CMOS filter causing in-band and out-of-band nonlinear distortions. The improved performance of the proposed model is demonstrated with circuital simulations of a 10th-order band pass filter, realized using a five-stage Gm-C Biquad cascade, and validated using out-of-sample sinusoidal and QAM signals. The same technique is extended to an array receiver with mismatched channels' responses showing that digital calibration can compensate the loss of directivity and enhance the overall system SFDR. An iterative backward pruning is applied to the Volterra models showing that complexity can be reduced without impacting linearity, obtaining state-of-the-art accuracy/complexity performance. Calibration of Time-Interleaved ADCs, widely used in RF-to-digital wideband receivers, is carried out developing ad hoc models because the steep discontinuities generated by the imperfect canceling of aliasing would require a huge number of terms in a polynomial approximation. A closed-form solution is derived for a 4-channel TI-ADC affected by gain errors and timing skews solving the perfect reconstruction equations. A background calibration technique is presented based on cyclo-stationary filter banks architecture. Convergence speed and accuracy of the recursive algorithm are discussed and complexity reduction techniques are applied

Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso