Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.Agencia Estatal de Investigación PID2019-107258RB-C32Unión Europea PID2019-107258RB-C3

Energy-efficient amplifiers based on quasi-floating gate techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.This research was funded by AEI/FEDER, grant number PID2019-107258RB-C32

CMOS Design of Reconfigurable SoC Systems for Impedance Sensor Devices

La rápida evolución en el campo de los sensores inteligentes, junto con los avances en las tecnologías de la computación y la comunicación, está revolucionando la forma en que recopilamos y analizamos datos del mundo físico para tomar decisiones, facilitando nuevas soluciones que desempeñan tareas que antes eran inconcebibles de lograr.La inclusión en un mismo dado de silicio de todos los elementos necesarios para un proceso de monitorización y actuación ha sido posible gracias a los avances en micro (y nano) electrónica. Al mismo tiempo, la evolución de las tecnologías de procesamiento y micromecanizado de superficies de silicio y otros materiales complementarios ha dado lugar al desarrollo de sensores integrados compatibles con CMOS, lo que permite la implementación de matrices de sensores de alta densidad. Así, la combinación de un sistema de adquisición basado en sensores on-Chip, junto con un microprocesador como núcleo digital donde se puede ejecutar la digitalización de señales, el procesamiento y la comunicación de datos proporciona características adicionales como reducción del coste, compacidad, portabilidad, alimentación por batería, facilidad de uso e intercambio inteligente de datos, aumentando su potencial número de aplicaciones.Esta tesis pretende profundizar en el diseño de un sistema portátil de medición de espectroscopía de impedancia de baja potencia operado por batería, basado en tecnologías microelectrónicas CMOS, que pueda integrarse con el sensor, proporcionando una implementación paralelizable sin incrementar significativamente el tamaño o el consumo, pero manteniendo las principales características de fiabilidad y sensibilidad de un instrumento de laboratorio. Esto requiere el diseño tanto de la etapa de gestión de la energía como de las diferentes celdas que conforman la interfaz, que habrán de satisfacer los requisitos de un alto rendimiento a la par que las exigentes restricciones de tamaño mínimo y bajo consumo requeridas en la monitorización portátil, características que son aún más críticas al considerar la tendencia actual hacia matrices de sensores.A nivel de celdas, se proponen diferentes circuitos en un proceso CMOS de 180 nm: un regulador de baja caída de voltaje como unidad de gestión de energía, que proporciona una alimentación de 1.8 V estable, de bajo ruido, precisa e independiente de la carga para todo el sistema; amplificadores de instrumentación con una aproximación completamente diferencial, que incluyen una etapa de entrada de voltaje/corriente configurable, ganancia programable y ancho de banda ajustable, tanto en la frecuencia de corte baja como alta; un multiplicador para conformar la demodulación dual, que está embebido en el amplificador para optimizar consumo y área; y filtros pasa baja totalmente integrados, que actúan como extractores de magnitud de DC, con frecuencias de corte ajustables desde sub-Hz hasta cientos de Hz.<br /

A Photoplethysmography System Optimised for Pervasive Cardiac Monitoring

Photoplethysmography is a non-invasive sensing technique which infers instantaneous cardiac function from an optical measurement of blood vessels. This thesis presents a photoplethysmography based sensor system that has been developed speci fically for the requirements of a pervasive healthcare monitoring system. Continuous monitoring of patients requires both the size and power consumption of the chosen sensor solution to be minimised to ensure the patients will be willing to use the device. Pervasive sensing also requires that the device be scalable for manufacturing in high volume at a build cost that healthcare providers are willing to accept. System level choice of both electronic circuits and signal processing techniques are based on their sensitivity to cardiac biosignals, robustness against noise inducing artefacts and simplicity of implementation. Numerical analysis is used to justify the implementation of a technique in hardware. Circuit prototyping and experimental data collection is used to validate a technique's application. The entire signal chain operates in the discrete-time domain which allows all of the signal processing to be implemented in firmware on an embedded processor which minimised the number of discrete components while optimising the trade-off between power and bandwidth in the analogue front-end. Synchronisation of the optical illumination and detection modules enables high dynamic range rejection of both AC and DC independent light sources without compromising the biosignal. Signal delineation is used to reduce the required communication bandwidth as it preserves both amplitude and temporal resolution of the non-stationary photoplethysmography signals allowing more complicated analytical techniques to be performed at the other end of communication channel. The complete sensing system is implemented on a single PCB using only commercial-off -the-shelf components and consumes less than 7.5mW of power. The sensor platform is validated by the successful capture of physiological data in a harsh optical sensing environment

A Photoplethysmography System Optimised for Pervasive Cardiac Monitoring

Photoplethysmography is a non-invasive sensing technique which infers instantaneous cardiac function from an optical measurement of blood vessels. This thesis presents a photoplethysmography based sensor system that has been developed speci fically for the requirements of a pervasive healthcare monitoring system. Continuous monitoring of patients requires both the size and power consumption of the chosen sensor solution to be minimised to ensure the patients will be willing to use the device. Pervasive sensing also requires that the device be scalable for manufacturing in high volume at a build cost that healthcare providers are willing to accept. System level choice of both electronic circuits and signal processing techniques are based on their sensitivity to cardiac biosignals, robustness against noise inducing artefacts and simplicity of implementation. Numerical analysis is used to justify the implementation of a technique in hardware. Circuit prototyping and experimental data collection is used to validate a technique's application. The entire signal chain operates in the discrete-time domain which allows all of the signal processing to be implemented in firmware on an embedded processor which minimised the number of discrete components while optimising the trade-off between power and bandwidth in the analogue front-end. Synchronisation of the optical illumination and detection modules enables high dynamic range rejection of both AC and DC independent light sources without compromising the biosignal. Signal delineation is used to reduce the required communication bandwidth as it preserves both amplitude and temporal resolution of the non-stationary photoplethysmography signals allowing more complicated analytical techniques to be performed at the other end of communication channel. The complete sensing system is implemented on a single PCB using only commercial-off -the-shelf components and consumes less than 7.5mW of power. The sensor platform is validated by the successful capture of physiological data in a harsh optical sensing environment

High-precision fluorescence photometry for real-time biomarkers detection

Les derniers évènements planétaires et plus particulièrement l'avènement sans précédent du nouveau coronavirus augmente la demande pour des appareils de test à proximité du patient. Ceux-ci fonctionnent avec une batterie et peuvent identifier rapidement des biomarqueurs cibles. Pareils systèmes permettent aux utilisateurs, disposant de connaissances limitées en la matière, de réagir rapidement, par exemple dans la détection d'un cas positif de COVID-19. La mise en œuvre de l'élaboration d'un tel instrument est un projet multidisciplinaire impliquant notamment la conception de circuits intégrés, la programmation, la conception optique et la biologie, demandant tous une maîtrise pointue des détails. De plus, l'établissement des spécifications et des exigences pour mesurer avec précision les interactions lumière-échantillon s'additionnent au besoin d'expérience dans la conception et la fabrication de tels systèmes microélectriques personnalisés et nécessitent en elles-mêmes, une connaissance approfondie de la physique et des mathématiques. Ce projet vise donc à concevoir et à mettre en œuvre un appareil sans fil pour détecter rapidement des biomarqueurs impliqués dans des maladies infectieuses telles que le COVID-19 ou des types de cancers en milieu ambulatoire. Cette détection se fait grâce à des méthodes basées sur la fluorescence. La spectrophotométrie de fluorescence permet aux médecins d'identifier la présence de matériel génétique viral ou bactérien tel que l'ADN ou l'ARN et de les caractériser. Les appareils de paillasse sont énormes et gourmand énergétiquement tandis que les spectrophotomètres à fluorescence miniatuarisés disponibles dans le commerce sont confrontés à de nombreux défis. Ces appareils miniaturisés ont été découverts en tirant parti des diodes électroluminescentes (DEL) à semi-conducteurs peu coûteuses et de la technologie des circuits intégrés. Ces avantages aident les scientifiques à réduire les erreurs possibles, la consommation d'énergie et le coût du produit final utilisé par la population. Cependant, comme leurs homologues de paillasse, ces appareils POC doivent quantifier les concentrations en micro-volume d'analytes sur une large gamme de longueurs d'onde suivant le cadre d'une économie en ressources. Le microsystème envisagé bénéficie d'une approche de haute précision pour fabriquer une puce microélectronique CMOS. Ce procédé se fait de concert avec un boîtier personnalisé imprimé en 3D pour réaliser le spectrophotomètre à la fluorescence nécessaire à la détection quantitative d'analytes en microvolume. En ce qui a trait à la conception de circuits, une nouvelle technique de mise à auto-zeroing est appliquée à l'amplificateur central, celui-ci étant linéarisé avec des techniques de recyclage et de polarisation adaptative. Cet amplificateur central est entièrement différentiel et est utilisé dans un amplificateur à verrouillage pour récupérer le signal d'intérêt éclipsé par le bruit. De plus, l'augmentation de la sensibilité de l'appareil permet des mesures quantitatives avec des concentrations en micro-volume d'analytes ayant moins d'erreurs de prédiction de concentration. Cet avantage cumulé à une faible consommation d'énergie, un faible coût, de petites dimensions et un poids léger font de notre appareil une solution POC prometteuse dans le domaine de la spectrophotométrie de fluorescence. La validation de ce projet s'est fait en concevant, fabriquant et testant un prototype discret et sans fil. Son article de référence a été publié dans IEEE LSC 2018. Quant à la caractérisation et l'interprétation du prototype d'expériences in vitro à l'aide d'une interface MATLAB personnalisée, cet article a été publié dans IEEE Sensors journal (2021). Les circuits intégrés et les photodétecteurs ont été fabriqués ont été conçus et fabriqués par Cadence en 2019. Relativement aux solutions de circuit proposées, elles ont été fabriquées avec la technologie CMOS 180 nm et publiées lors de la conférence IEEE MWSCAS 2020. Tout comme cette dernière contribution, les expériences in vitro avec le dispositif proposé incluant la puce personnalisée et le boîtier imprimé en 3D ont été réalisés et les résultats électriques et optiques ont été soumis au IEEE Journal of Solid-State Circuits (JSSC 2022).The most recent and unprecedented experience of the novel coronavirus increases the demand for battery-operated near-patient testing devices that can rapidly identify the target biomarkers. Such systems enable end-users with limited resources to quickly get feedback on various medical tests, such as detecting positive COVID-19 cases. Implementing such a device is a multidisciplinary project dealing with multiple areas of expertise, including integrated circuit design, programming, optical design, and biology, each of which needs a firm grasp of details. Alongside the need for experience in designing and manufacturing custom microelectronic systems, establishing the specifications and requirements to precisely measure the light-sample interactions requires an in-depth knowledge of physics and mathematics. This project aims to design and implement a wireless point-of-care (POC) device to rapidly detect biomarkers involved in infectious diseases such as COVID-19 or different types of cancers in an ambulatory setting using fluorescence-based methods. Fluorescence spectrophotometry allows physicians to identify and characterize viral or bacterial genetic materials such as DNAs or RNAs. The benchtop devices that are currently available are bulky and power-hungry, whereas the commercially available miniaturized fluorescence spectrophotometers are facing many challenges. Many of these difficulties have been resolved in literature thanks to inexpensive semiconductor light-emitting diodes (LEDs) and integrated circuits technology. Such advantages aid scientists in decreasing the size, power consumption, and cost of the final product for end-users. However, like the benchtop counterparts, such POC devices must quantify micro-volume concentrations of analytes across a wide wave length range under an economy of resources. The envisioned microsystem benefits from a high-precision approach to fabricating a CMOS microelectronic chip combined with a custom 3D-printed housing. This implementation results in a fluorescence spectrophotometer for qualitative and quantitative detection of micro-volume analytes. In terms of circuit design, a novel switched-biasing ping-pong auto-zeroed technique is applied to the core amplifier, linearized with recycling and adaptive biasing techniques. The fully differential core amplifier is utilized within a lock-in amplifier to retrieve the signal of interest overshadowed by noise. Increasing the device's sensitivity allows quantitative measurements down to micro-volume concentrations of analytes with less concentration prediction error. Such an advantage, along with low-power consumption, low cost, low weight, and small dimensions, make our device a promising POC solution in the fluorescence spectrophotometry area. The approach of this project was validated by designing, fabricating, and testing a discrete and wireless prototype. Its conference paper was published in IEEE LSC 2018, and the prototype characterization and interpretation of in vitro experiments using a custom MATLAB interface were published in IEEE Sensors Journal (2021). The integrated circuits and photodetectors were designed and fabricated by the Cadence circuit design toolbox (2019). The proposed circuit solutions were fabricated with 180-nm CMOS technology and published at IEEE MWSCAS 2020 conference. As the last contribution, the in vitro experiments with the proposed device, including the custom chip and 3D-printed housing, were performed, and the electrical and optical results were submitted to the IEEE Journal of Solid-State Circuits (JSSC 2022)

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

RF Amplification and Filtering Techniques for Cellular Receivers

The usage of various wireless standards, such as Bluetooth, Wi-Fi, GPS, and 4G/5G cellular, has been continually increasing. In order to utilize the frequency bands efficiently and to support new communication standards with lower power consumption, lower occupied volume and at reduced costs, multimode transceivers, software defined radios (SDRs), cognitive radios, etc., have been actively investigated. Broadband behavior of a wireless receiver is typically defined by its front-end low-noise amplifier (LNA), whose design must consider trade-offs between input matching, noise figure (NF), gain, bandwidth, linearity, and voltage headroom in a given process technology. Moreover, monolithic RF wireless receivers have been trending toward high intermediatefrequency (IF) or superhetrodyne radios thanks to recent breakthroughs in silicon integration of band-pass channel-select filters. The main motivation is to avoid the common issues in the currently predominant zero/low-IF receivers, such as poor 2nd-order nonlinearity, sensitivity to 1/f (i.e. flicker) noise and time-variant dc offsets, especially in the fine CMOS technology. To avoid interferers and blockers at the susceptible image frequencies that the high-IF entails, band-pass filters (BPF) with high quality (Q) factor components for sharp transfer-function transition characteristics are now required. In addition, integrated low-pass filters (LPF) with strong rejection of out-of-band frequency components are essential building blocks in a variety of applications, such as telecommunications, video signal processing, anti-aliasing filtering, etc. Attention is drawn toward structures featuring low noise, small area, high in-/out-of-band linearity performance, and low-power consumption. This thesis comprises three main parts. In the first part (Chapters 2 and 3), we focus on the design and implementation of several innovative wideband low-noise (transconductance) amplifiers [LN(T)A] for wireless cellular applications. In the first design, we introduce new approaches to reduce the noise figure of the noise-cancellation LNAs without sacrificing the power consumption budget, which leads to NF of 2 dB without adding extra power consumption. The proposed LNAs also have the capability to be used in current-mode receivers, especially in discrete-time receivers, as in the form of low noise transconductance amplifier (LNTA). In the second design, two different two-fold noise cancellation approaches are proposed, which not only improve the noise performance of the design, but also achieve high linearity (IIP3=+4.25 dBm). The proposed LN(T)As are implemented in TSMC 28-nm LP CMOS technology to prove that they are suitable for applications such as sub-6 GHz 5G receivers. The second objective of this dissertation research is to invent a novel method of band-pass filtering, which leads to achieving very sharp and selective band-pass filtering with high linearity and low input referred (IRN) noise (Chapter 4). This technique improves the noise and linearity performance without adding extra clock phases. Hence, the duty cycle of the clock phases stays constant, despite the sophisticated improvements. Moreover, due to its sharp filtering, it can filter out high blockers of near channels and can increase the receiver’s blocker tolerance. With the same total capacitor size and clock duty cycle as in a 1st-order complex charge-sharing band-pass filter (CS BPF), the proposed design achieves 20 dB better out-of-band filtering compared to the prior-art 1st-order CS BPF and 10 dB better out-of-band filtering compared to the conventional 2nd-order C-CS BPF. Finally, the stop-band rejection of the discrete-time infinite-impulse response (IIR) lowpass filter is improved by applying a novel technique to enhance the anti-aliasing filtering (Chapter 5). The aim is to introduce a 4th-order charge rotating (CR) discrete-time (DT) LPF, which achieves the record of stop-band rejection of 120 dB by using a novel pseudolinear interpolation technique while keeping the sampling frequency and the capacitor values constant

Development, Characterization and Operation of the DCDB, the Front-End Readout Chip for the Pixel Vertex Detector of the Future BELLE-II Experiment

The BELLE-II detector is the upgrade of its predecessor named BELLE at KEK research centre in Tsukuba, Japan, which was successfully used in the past to find evidence for CP violating decays. The upgraded SuperKEKB accelerator is specified to produce a luminosity of 8*10^35 cm^-2 s^-1. Consequently, the BELLE-II detector and particularly the innermost pixel vertex detector (PXD) suffers from enormous occupancy due to background events. Coping with this harsh environment while providing the required physics performance results in tough specifications for the front-end readout electronics. The PXD pixel detector system is based on the DEPFET technology. DEPFET transistors combine particle detection and signal amplification within one device. The DCDB chip is developed to sample and digitize signals from these transistors while complying with the specifications of BELLE-II. The presented work illustrates the chip’s features and describes its implementation process. The device is comprehensively characterized using an individually developed test environment. The obtained results are presented. The DCDB’s ability to serve as a readout device for particle physics applications is demonstrated by its successful operation within a DEPFET detector prototype system. Highlights are a decay spectrum measurement using Cd-109 and the successful operation in a beam test experiment at CERN