Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures

Component-Level Electronic-Assembly Repair (CLEAR) System Architecture

This document captures the system architecture for a Component-Level Electronic-Assembly Repair (CLEAR) capability needed for electronics maintenance and repair of the Constellation Program (CxP). CLEAR is intended to improve flight system supportability and reduce the mass of spares required to maintain the electronics of human rated spacecraft on long duration missions. By necessity it allows the crew to make repairs that would otherwise be performed by Earth based repair depots. Because of practical knowledge and skill limitations of small spaceflight crews they must be augmented by Earth based support crews and automated repair equipment. This system architecture covers the complete system from ground-user to flight hardware and flight crew and defines an Earth segment and a Space segment. The Earth Segment involves database management, operational planning, and remote equipment programming and validation processes. The Space Segment involves the automated diagnostic, test and repair equipment required for a complete repair process. This document defines three major subsystems including, tele-operations that links the flight hardware to ground support, highly reconfigurable diagnostics and test instruments, and a CLEAR Repair Apparatus that automates the physical repair process

Graphonomics and your Brain on Art, Creativity and Innovation : Proceedings of the 19th International Graphonomics Conference (IGS 2019 – Your Brain on Art)

[Italiano]: “Grafonomia e cervello su arte, creatività e innovazione”. Un forum internazionale per discutere sui recenti progressi nell'interazione tra arti creative, neuroscienze, ingegneria, comunicazione, tecnologia, industria, istruzione, design, applicazioni forensi e mediche. I contributi hanno esaminato lo stato dell'arte, identificando sfide e opportunità, e hanno delineato le possibili linee di sviluppo di questo settore di ricerca. I temi affrontati includono: strategie integrate per la comprensione dei sistemi neurali, affettivi e cognitivi in ambienti realistici e complessi; individualità e differenziazione dal punto di vista neurale e comportamentale; neuroaesthetics (uso delle neuroscienze per spiegare e comprendere le esperienze estetiche a livello neurologico); creatività e innovazione; neuro-ingegneria e arte ispirata dal cervello, creatività e uso di dispositivi di mobile brain-body imaging (MoBI) indossabili; terapia basata su arte creativa; apprendimento informale; formazione; applicazioni forensi. / [English]: “Graphonomics and your brain on art, creativity and innovation”. A single track, international forum for discussion on recent advances at the intersection of the creative arts, neuroscience, engineering, media, technology, industry, education, design, forensics, and medicine. The contributions reviewed the state of the art, identified challenges and opportunities and created a roadmap for the field of graphonomics and your brain on art. The topics addressed include: integrative strategies for understanding neural, affective and cognitive systems in realistic, complex environments; neural and behavioral individuality and variation; neuroaesthetics (the use of neuroscience to explain and understand the aesthetic experiences at the neurological level); creativity and innovation; neuroengineering and brain-inspired art, creative concepts and wearable mobile brain-body imaging (MoBI) designs; creative art therapy; informal learning; education; forensics

Built-in-self-test of RF front-end circuitry

Fuelled by the ever increasing demand for wireless products and the advent of deep submicron CMOS, RF ICs have become fairly commonplace in the semiconductor market. This has given rise to a new breed of Systems-On-Chip (SOCs) with RF front-ends tightly integrated along with digital, analog and mixed signal circuitry. However, the reliability of the integrated RF front-end continues to be a matter of significant concern and considerable research. A major challenge to the reliability of RF ICs is the fact that their performance is also severely degraded by wide tolerances in on-chip passives and package parasitics, in addition to process related faults. Due to the absence of contact based testing solutions in embedded RF SOCs (because the very act of probing may affect the performance of the RF circuit), coupled with the presence of very few test access nodes, a Built In Self Test approach (BiST) may prove to be the most efficient test scheme. However due to the associated challenges, a comprehensive and low-overhead BiST methodology for on-chip testing of RF ICs has not yet been reported in literature. In the current work, an approach to RF self-test that has hitherto been unexplored both in literature and in the commercial arena is proposed. A sensitive current monitor has been used to extract variations in the supply current drawn by the circuit-under-test (CUT). These variations are then processed in time and frequency domain to develop signatures. The acquired signatures can then be mapped to specific behavioral anomalies and the locations of these anomalies. The CUT is first excited by simple test inputs that can be generated on-chip. The current monitor extracts the corresponding variations in the supply current of the CUT, thereby creating signatures that map to various performance metrics of the circuit. These signatures can then be post-processed by low overhead on-chip circuitry and converted into an accessible form. To be successful in the RF domain any BIST architecture must be minimally invasive, reliable, offer good fault coverage and present low real estate and power overheads. The current-based self-test approach successfully addresses all these concerns. The technique has been applied to RF Low Noise Amplifiers, Mixers and Voltage Controlled Oscillators. The circuitry and post-processing techniques have also been demonstrated in silicon (using the IBM 0.25 micron RF CMOS process). The entire self-test of the RF front-end can be accomplished with a total test time of approximately 30µs, which is several orders of magnitude better than existing commercial test schemes

Space shuttle propulsion systems on-board checkout and monitoring system development study. Volume 1 - Summary Final report

Development of onboard checkout equipment and performance monitoring capability for space shuttles - Vol.

Auto detection in autism

Autism is a neurobiological disorder in which, certain regions of the brain are affected. The main features of autism are impairment in communication, social interaction, language and deficit in imitation and theory of mind. Using Functional Magnetic Resonance Imaging (fMRI), haemodynamic responses during a bilateral finger tapping task are analyzed for both autistic subjects and normal control subjects. fMRI is a noninvasive technique to image the activity of the brain related to a specific task. Generally, the active voxels in the IMRI images are detected using parametric or non-parametric statistical methods in which the fMRI response is assumed to have a model. Such methods are not applicable to detect the active voxels when the fMRI response is unknown. The data driven methods are also used for analyzing the fMRI data. The data driven methods are computationally expensive. In this study, a method for detecting activated voxels without using prior knowledge of the input stimulus is presented. The assumption in this method is that the activation typically involves larger region comprising of several voxels and that these neighboring activated voxels are also temporally correlated. To validate the accuracy of this method, Principal component Analysis and Independent Component Analysis are also performed. A significant overlap in the sensorimotor cortex is found between the various methods suggesting that the automatic detecting method presented does provide accurate detection and localization

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Mechanical systems readiness assessment and performance monitoring study

The problem of mechanical devices which lack the real-time readiness assessment and performance monitoring capability required for future space missions is studied. The results of a test program to establish the feasibility of implementing structure borne acoustics, a nondestructive test technique, are described. The program included the monitoring of operational acoustic signatures of five separate mechanical components, each possessing distinct sound characteristics. Acoustic signatures were established for normal operation of each component. Critical failure modes were then inserted into the test components, and faulted acoustic signatures obtained. Predominant features of the sound signature were related back to operational events occurring within the components both for normal and failure mode operations. All of these steps can be automated. The structure borne acoustics technique lends itself to reducing checkout time, simplifying maintenance procedures, and reducing manual involvement in the checkout, operation, maintenance, and fault diagnosis of mechanical systems

Design, Fabrication and Veri cation of a Mixed-Signal XY Zone Monitoring Circuit and its Application to a Phase Lock Loop Circuit

El presente proyecto de final de carrera se centra en el diseño, análisis e implementación en silicio de una metodología de test/diagnosis basada en la comparación de firmas digitales generadas a partir de curvas de Lissajous. Se muestra su aplicación para testar la etapa de filtro de un circuito de bucle de enganche de fase (phase lock loop, PLL), así como los resultados experimentales de su implementación en tecnología CMOS de 65 nm. La obtención de las firmas digitales se consigue mediante el uso de un circuito monitor, el cual, a partir de la composición de dos señales periódicas del circuito a analizar, genera, para cada punto de la curva de Lissajous, un valor digital. La utilización de varios monitores con gurados de la manera adecuada permite una completa teselación del plano en diferentes zonas y por tanto, la generación de distintos códigos digitales (firma) a medida que la curva de Lissajous evoluciona en el tiempo. El test del circuito y/o diagnosis del posible defecto se realiza mediante la comparación de la signatura golden o sin defecto y la signatura generada por el circuito testado. Para la comparación de firmas se emplea el concepto de distancia de Hamming entre códigos a modo de métrica de discrepancia. A partir de los valores precalculados de la métrica para cada posible valor del defecto se consigue realizar la diagnosis de este para el parámetro en estudio. El trabajo se enmarca en el diseño de circuitos integrados de muy alta escala de integración usando una tecnología CMOS de actualidad (65 nm). Es por ello que se requieren técnicas de diseño analógico específicas, como lo son las estrategias centroidales para la elaboración de layouts o el correcto modelado de transistores nanométricos. Para esto último se hace uso del modelo Berkeley, el cual, debidamente ajustado a la tecnología empleada, proporciona aproximaciones muy aceptables y con relativa facilidad de uso. Con el objetivo de verificar la metodología de test/diagnosis propuesta, se hace uso de una aplicación Matlab que permite simular el comportamiento del circuito a testar en diferentes situaciones. Es posible excitar el circuito con distintas entradas, cambiar los parámetros de este, introducir defectos, o emplear distintos conjuntos de curvas para teselar el plano. La aplicación resulta fundamental para efectuar el proceso de diagnosis pues relaciona la cantidad de defecto con los valores de discrepancia obtenidos con la métrica definida. Finalmente, se presentan los resultados experimentales obtenidos con el chip fabricado. Se constata el correcto comportamiento de este y la validez de la metodología de test/diagnosis propuesta