SAT-based Automatic Test Pattern Generation

Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for Automatic Test Pattern Generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on Conjunctive Normal Forms (CNF), the problem has to be transformed. During transformation, relevant information about the problem might get lost and therefore is not available in the solving process. In the following we briefly motivate the problem and provide the latest developments in the field. The technique was implemented and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. Significant improvements in overall performance and robustness are demonstrated

EFFICIENCY TEST OF AUTOMATIC TEST PATTERN GENERATION METHODS

Automatic Test Pattern Generation (ATPG) is unavoidable for large combinational circuits, However, since ATPG is a known NP-complet problem, this is a very CPU-time consuming process, Therefore choosing the optimal ATPG algorithm for an industrial test generation system can be an important question, However, this question cannot be easily answered because of the implementational and evaluation differences of the published algorithms, This paper presents a software frame, where any ATPG method and their heuristic can be easily implemented allowing a correct comparison between different methods, On the other hand the known ATPG methods cannot be ordered by quality, because their efficiency depends on the properties of the examined circuit. Therefore it seems to be reasonable to develop a hibrid strategy whose effectivity is independent of the circuit properties and near to the known strategies, The presented frame is an ideal environment for developing such a new method, Experimental results are also presented on some implemented algorithms and heuristics using a variety of MSI components and ISCAS'85 benchmark circuits

Automatic Test Pattern Generation for Robust Quantum Circuit Testing

Quantum circuit testing is essential for detecting potential faults in realistic quantum devices, while the testing process itself also suffers from the inexactness and unreliability of quantum operations. This paper alleviates the issue by proposing a novel framework of automatic test pattern generation (ATPG) for the robust quantum circuit testing. We introduce the stabilizer projector decomposition (SPD) for representing the quantum test pattern, and construct the test application using Clifford-only circuits, which are rather robust and efficient as evidenced in the fault-tolerant quantum computation. However, it is generally hard to generate SPDs due to the exponentially growing number of the stabilizer projectors. To circumvent this difficulty, we develop an SPD generation algorithm, as well as several acceleration techniques which can exploit both locality and sparsity in generating SPDs. The effectiveness of our algorithms are validated by 1) theoretical guarantees under reasonable conditions, 2) experimental results on commonly used benchmark circuits, such as Quantum Fourier Transform (QFT), Quantum Volume (QV) and Bernstein-Vazirani (BV) in IBM Qiskit. For example, test patterns are automatically generated by our algorithm for a 10-qubit QFT circuit, and then a fault is detected by simulating the test application with detection accuracy higher than 91%.Comment: 18 pages, 6 figures, 3 table

SAT-based Automatic Test Pattern Generation

Abstract. Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for Automatic Test Pattern Generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on Conjunctive Normal Forms (CNF), the problem has to be transformed. During transformation, relevant information about the problem might get lost and therefore is not available in the solving process. In the following we briefly motivate the problem and provide the latest developments in the field. The technique was implemented and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. Significant improvements in overall performance and robustness are demonstrated

Standard Transistor Array (STAR). Volume 2: Test pattern generation

Testing of large scale integrated logic circuits is considered from the point-of-view of automatic test pattern generation. A logic simulator based approach for automatic test pattern generation is taken and is described. The logic model and the timing model used in the simulator are also described. Two methods are presented for generating test patterns from the output of the simulator. Recommendations for future study are also presented

Automatic test pattern generation for asynchronous circuits

The testability of integrated circuits becomes worse with transistor dimensions reaching nanometer scales. Testing, the process of ensuring that circuits are fabricated without defects, becomes inevitably part of the design process; a technique called design for test (DFT). Asynchronous circuits have a number of desirable properties making them suitable for the challenges posed by modern technologies, but are severely limited by the unavailability of EDA tools for DFT and automatic test-pattern generation (ATPG). This thesis is motivated towards developing test generation methodologies for asynchronous circuits. In total four methods were developed which are aimed at two different fault models: stuck-at faults at the basic logic gate level and transistor-level faults. The methods were evaluated using a set of benchmark circuits and compared favorably to previously published work. First, ABALLAST is a partial-scan DFT method adapting the well-known BALLAST technique for asynchronous circuits where balanced structures are used to guide the selection of the state-holding elements that will be scanned. The test inputs are automatically provided by a novel test pattern generator, which uses time frame unrolling to deal with the remaining, non-scanned sequential C-elements. The second method, called AGLOB, uses algorithms from strongly-connected components in graph graph theory as a method for finding the optimal position of breaking the loops in the asynchronous circuit and adding scan registers. The corresponding ATPG method converts cyclic circuits into acyclic for which standard tools can provide test patterns. These patterns are then automatically converted for use in the original cyclic circuits. The third method, ASCP, employs a new cycle enumeration method to find the loops present in a circuit. Enumerated cycles are then processed using an efficient set covering heuristic to select the scan elements for the circuit to be tested.Applying these methods to the benchmark circuits shows an improvement in fault coverage compared to previous work, which, for some circuits, was substantial. As no single method consistently outperforms the others in all benchmarks, they are all valuable as a designer’s suite of tools for testing. Moreover, since they are all scan-based, they are compatible and thus can be simultaneously used in different parts of a larger circuit. In the final method, ATRANTE, the main motivation of developing ATPG is supplemented by transistor level test generation. It is developed for asynchronous circuits designed using a State Transition Graph (STG) as their specification. The transistor-level circuit faults are efficiently mapped onto faults that modify the original STG. For each potential STG fault, the ATPG tool provides a sequence of test vectors that expose the difference in behavior to the output ports. The fault coverage obtained was 52-72 % higher than the coverage obtained using the gate level tests. Overall, four different design for test (DFT) methods for automatic test pattern generation (ATPG) for asynchronous circuits at both gate and transistor level were introduced in this thesis. A circuit extraction method for representing the asynchronous circuits at a higher level of abstraction was also implemented. Developing new methods for the test generation of asynchronous circuits in this thesis facilitates the test generation for asynchronous designs using the CAD tools available for testing the synchronous designs. Lessons learned and the research questions raised due to this work will impact the future work to probe the possibilities of developing robust CAD tools for testing the future asynchronous designs

Scan Test Coverage Improvement Via Automatic Test Pattern Generation (Atpg) Tool Configuration

The scan test coverage improvement by using automatic test pattern generation (ATPG) tool configuration was investigated. Improving the test coverage is essential in detecting manufacturing defects in semiconductor industry so that high quality products can be supplied to consumers. The ATPG tool used was Mentor Graphics Tessent TestKompress (version 2014.1). The study was done by setting up a few experiments of utilizing and modifying ATPG commands and switches, observing the test coverage improvement from the statistical reports provided during pattern generation process and providing relatable discussions. By modifying the ATPG commands, it can be expected to have some improvement in the test coverage. The scan test patterns generated were stuck-at test patterns. Based on the experiments done, comparison was made on the different coverage readings and the most optimized method and flow of ATPG were determined. The most optimized flow gave an improvement of 0.91% in test coverage which is acceptable since this method does not involve a change in design. The test patterns generated were converted and tested using automatic test equipment (ATE) to observe its performance on real silicon. The test coverage improvement using ATPG tool instead of the design-based method is important as a faster workaround for back-end engineers to provide high quality test contents in such a short product development duration

Soft Computing Approach To Automatic Test Pattern Generation For Sequential Vlsi Circuit

Due to the constant development in the integrated circuits, the automatic test pattern generation problem become more vital for sequential vlsi circuits in these days. Also testing of integrating circuits and systems has become a difficult problem. In this paper we have discussed the problem of the automatic test sequence generation using particle swarm optimization(PSO) and technique for structure optimization of a deterministic test pattern generator using genetic algorithm(GA)

ATPG for Delay Defects in Current Mode Threshold Logic Circuits

An automatic test pattern generation approach todetect delay defects in a circuit consisting of current modethreshold logic gates is introduced. Each generated patternshould excite the maximum propagation delay at the fault site.Manufactured weights may vary, and maximum delay is ensuredby applying an appropriately generated set of patterns per fault.Experimental results show the efficiency of the proposed methods