High-performance hardware accelerators for image processing in space applications

Mars is a hard place to reach. While there have been many notable success stories in getting probes to the Red Planet, the historical record is full of bad news. The success rate for actually landing on the Martian surface is even worse, roughly 30%. This low success rate must be mainly credited to the Mars environment characteristics. In the Mars atmosphere strong winds frequently breath. This phenomena usually modifies the lander descending trajectory diverging it from the target one. Moreover, the Mars surface is not the best place where performing a safe land. It is pitched by many and close craters and huge stones, and characterized by huge mountains and hills (e.g., Olympus Mons is 648 km in diameter and 27 km tall). For these reasons a mission failure due to a landing in huge craters, on big stones or on part of the surface characterized by a high slope is highly probable. In the last years, all space agencies have increased their research efforts in order to enhance the success rate of Mars missions. In particular, the two hottest research topics are: the active debris removal and the guided landing on Mars. The former aims at finding new methods to remove space debris exploiting unmanned spacecrafts. These must be able to autonomously: detect a debris, analyses it, in order to extract its characteristics in terms of weight, speed and dimension, and, eventually, rendezvous with it. In order to perform these tasks, the spacecraft must have high vision capabilities. In other words, it must be able to take pictures and process them with very complex image processing algorithms in order to detect, track and analyse the debris. The latter aims at increasing the landing point precision (i.e., landing ellipse) on Mars. Future space-missions will increasingly adopt Video Based Navigation systems to assist the entry, descent and landing (EDL) phase of space modules (e.g., spacecrafts), enhancing the precision of automatic EDL navigation systems. For instance, recent space exploration missions, e.g., Spirity, Oppurtunity, and Curiosity, made use of an EDL procedure aiming at following a fixed and precomputed descending trajectory to reach a precise landing point. This approach guarantees a maximum landing point precision of 20 km. By comparing this data with the Mars environment characteristics, it is possible to understand how the mission failure probability still remains really high. A very challenging problem is to design an autonomous-guided EDL system able to even more reduce the landing ellipse, guaranteeing to avoid the landing in dangerous area of Mars surface (e.g., huge craters or big stones) that could lead to the mission failure. The autonomous behaviour of the system is mandatory since a manual driven approach is not feasible due to the distance between Earth and Mars. Since this distance varies from 56 to 100 million of km approximately due to the orbit eccentricity, even if a signal transmission at the light speed could be possible, in the best case the transmission time would be around 31 minutes, exceeding so the overall duration of the EDL phase. In both applications, algorithms must guarantee self-adaptability to the environmental conditions. Since the Mars (and in general the space) harsh conditions are difficult to be predicted at design time, these algorithms must be able to automatically tune the internal parameters depending on the current conditions. Moreover, real-time performances are another key factor. Since a software implementation of these computational intensive tasks cannot reach the required performances, these algorithms must be accelerated via hardware. For this reasons, this thesis presents my research work done on advanced image processing algorithms for space applications and the associated hardware accelerators. My research activity has been focused on both the algorithm and their hardware implementations. Concerning the first aspect, I mainly focused my research effort to integrate self-adaptability features in the existing algorithms. While concerning the second, I studied and validated a methodology to efficiently develop, verify and validate hardware components aimed at accelerating video-based applications. This approach allowed me to develop and test high performance hardware accelerators that strongly overcome the performances of the actual state-of-the-art implementations. The thesis is organized in four main chapters. Chapter 2 starts with a brief introduction about the story of digital image processing. The main content of this chapter is the description of space missions in which digital image processing has a key role. A major effort has been spent on the missions in which my research activity has a substantial impact. In particular, for these missions, this chapter deeply analizes and evaluates the state-of-the-art approaches and algorithms. Chapter 3 analyzes and compares the two technologies used to implement high performances hardware accelerators, i.e., Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs). Thanks to this information the reader may understand the main reasons behind the decision of space agencies to exploit FPGAs instead of ASICs for high-performance hardware accelerators in space missions, even if FPGAs are more sensible to Single Event Upsets (i.e., transient error induced on hardware component by alpha particles and solar radiation in space). Moreover, this chapter deeply describes the three available space-grade FPGA technologies (i.e., One-time Programmable, Flash-based, and SRAM-based), and the main fault-mitigation techniques against SEUs that are mandatory for employing space-grade FPGAs in actual missions. Chapter 4 describes one of the main contribution of my research work: a library of high-performance hardware accelerators for image processing in space applications. The basic idea behind this library is to offer to designers a set of validated hardware components able to strongly speed up the basic image processing operations commonly used in an image processing chain. In other words, these components can be directly used as elementary building blocks to easily create a complex image processing system, without wasting time in the debug and validation phase. This library groups the proposed hardware accelerators in IP-core families. The components contained in a same family share the same provided functionality and input/output interface. This harmonization in the I/O interface enables to substitute, inside a complex image processing system, components of the same family without requiring modifications to the system communication infrastructure. In addition to the analysis of the internal architecture of the proposed components, another important aspect of this chapter is the methodology used to develop, verify and validate the proposed high performance image processing hardware accelerators. This methodology involves the usage of different programming and hardware description languages in order to support the designer from the algorithm modelling up to the hardware implementation and validation. Chapter 5 presents the proposed complex image processing systems. In particular, it exploits a set of actual case studies, associated with the most recent space agency needs, to show how the hardware accelerator components can be assembled to build a complex image processing system. In addition to the hardware accelerators contained in the library, the described complex system embeds innovative ad-hoc hardware components and software routines able to provide high performance and self-adaptable image processing functionalities. To prove the benefits of the proposed methodology, each case study is concluded with a comparison with the current state-of-the-art implementations, highlighting the benefits in terms of performances and self-adaptability to the environmental conditions

Intermittent fault diagnosis and health monitoring for electronic interconnects

Literature survey and correspondence with industrial sector shows that No-Fault-Found (NFF) is a major concern in through life engineering services, especially for defence, aerospace, and other transport industry. There are various occurrences and root causes that result in NFF events but intermittent interconnections are the most frustrating. This is because it disappears while testing, and missed out by diagnostic equipment. This thesis describes the challenging and most important area of intermittent fault detection and health monitoring that focuses towards NFF situation in electronics interconnections. After introduction, this thesis starts with literature survey and describes financial impact on aerospace and other transport industry. It highlights NFF technologies and discuss different facts and their impact on NFF. Then It goes into experimental study that how repeatedly intermittent fault could be replicated. It describes a novel fault replicator that can generate repeatedly IFs for further experimental study on diagnosis techniques/algorithms. The novel IF replicator provide for single and multipoint intermittent connection. The experimental work focuses on mechanically induced intermittent conditions in connectors. This work illustrates a test regime that can be used to repeatedly reproduce intermittency in electronic connectors whilst subjected to vibration ... [cont.]

A conformance test framework for the DeviceNet fieldbus

The DeviceNet fieldbus technology is introduced and discussed. DeviceNet is an open standard fieldbus which uses the proven Controller Area Network technology. As an open standard fieldbus, the device conformance is extremely important to ensure smooth operation. The error management in DeviceNet protocol is highlighted and an error injection technique is devised to test the implementation under test for the correct error-recovery conformance. The designed Error Frame Generator prototype allows the error management and recovery of DeviceNet implementations to be conformance tested. The Error Frame Generator can also be used in other Controller Area Network based protocols. In addition, an automated Conformance Test Engine framework has been defined for realising the conformance testing of DeviceNet implementations. Automated conformance test is used to achieve consistent and reliable test results, apart from the benefits in time and personnel savings. This involves the investigations and feasibility studies in adapting the ISO 9646 conformance test standards for use in DeviceNet fieldbus. The Unique Input/Output sequences method is used for the generation of DeviceNet conformance tests. The Unique Input/Output method does not require a fully specified protocol specification and gives shorter test sequences, since only specific state information is needed. As conformance testing addresses only the protocol verification, it is foreseen that formal method validation of the DeviceNet protocol must be performed at some stage to validate the DeviceNet specification

Enhancing Real-time Embedded Image Processing Robustness on Reconfigurable Devices for Critical Applications

Nowadays, image processing is increasingly used in several application fields, such as biomedical, aerospace, or automotive. Within these fields, image processing is used to serve both non-critical and critical tasks. As example, in automotive, cameras are becoming key sensors in increasing car safety, driving assistance and driving comfort. They have been employed for infotainment (non-critical), as well as for some driver assistance tasks (critical), such as Forward Collision Avoidance, Intelligent Speed Control, or Pedestrian Detection. The complexity of these algorithms brings a challenge in real-time image processing systems, requiring high computing capacity, usually not available in processors for embedded systems. Hardware acceleration is therefore crucial, and devices such as Field Programmable Gate Arrays (FPGAs) best fit the growing demand of computational capabilities. These devices can assist embedded processors by significantly speeding-up computationally intensive software algorithms. Moreover, critical applications introduce strict requirements not only from the real-time constraints, but also from the device reliability and algorithm robustness points of view. Technology scaling is highlighting reliability problems related to aging phenomena, and to the increasing sensitivity of digital devices to external radiation events that can cause transient or even permanent faults. These faults can lead to wrong information processed or, in the worst case, to a dangerous system failure. In this context, the reconfigurable nature of FPGA devices can be exploited to increase the system reliability and robustness by leveraging Dynamic Partial Reconfiguration features. The research work presented in this thesis focuses on the development of techniques for implementing efficient and robust real-time embedded image processing hardware accelerators and systems for mission-critical applications. Three main challenges have been faced and will be discussed, along with proposed solutions, throughout the thesis: (i) achieving real-time performances, (ii) enhancing algorithm robustness, and (iii) increasing overall system's dependability. In order to ensure real-time performances, efficient FPGA-based hardware accelerators implementing selected image processing algorithms have been developed. Functionalities offered by the target technology, and algorithm's characteristics have been constantly taken into account while designing such accelerators, in order to efficiently tailor algorithm's operations to available hardware resources. On the other hand, the key idea for increasing image processing algorithms' robustness is to introduce self-adaptivity features at algorithm level, in order to maintain constant, or improve, the quality of results for a wide range of input conditions, that are not always fully predictable at design-time (e.g., noise level variations). This has been accomplished by measuring at run-time some characteristics of the input images, and then tuning the algorithm parameters based on such estimations. Dynamic reconfiguration features of modern reconfigurable FPGA have been extensively exploited in order to integrate run-time adaptivity into the designed hardware accelerators. Tools and methodologies have been also developed in order to increase the overall system dependability during reconfiguration processes, thus providing safe run-time adaptation mechanisms. In addition, taking into account the target technology and the environments in which the developed hardware accelerators and systems may be employed, dependability issues have been analyzed, leading to the development of a platform for quickly assessing the reliability and characterizing the behavior of hardware accelerators implemented on reconfigurable FPGAs when they are affected by such faults

Embedded computing systems design: architectural and application perspectives

Questo elaborato affronta varie problematiche legate alla progettazione e all'implementazione dei moderni sistemi embedded di computing, ponendo in rilevo, e talvolta in contrapposizione, le sfide che emergono all'avanzare della tecnologia ed i requisiti che invece emergono a livello applicativo, derivanti dalle necessità degli utenti finali e dai trend di mercato. La discussione sarà articolata tenendo conto di due punti di vista: la progettazione hardware e la loro applicazione a livello di sistema. A livello hardware saranno affrontati nel dettaglio i problemi di interconnettività on-chip. Aspetto che riguarda la parallelizzazione del calcolo, ma anche l'integrazione di funzionalità eterogenee. Sarà quindi discussa un'architettura d'interconnessione denominata Network-on-Chip (NoC). La soluzione proposta è in grado di supportare funzionalità avanzate di networking direttamente in hardware, consentendo tuttavia di raggiungere sempre un compromesso ottimale tra prestazioni in termini di traffico e requisiti di implementazioni a seconda dell'applicazione specifica. Nella discussione di questa tematica, verrà posto l'accento sul problema della configurabilità dei blocchi che compongono una NoC. Quello della configurabilità, è un problema sempre più sentito nella progettazione dei sistemi complessi, nei quali si cerca di sviluppare delle funzionalità, anche molto evolute, ma che siano semplicemente riutilizzabili. A tale scopo sarà introdotta una nuova metodologia, denominata Metacoding che consiste nell'astrarre i problemi di configurabilità attraverso linguaggi di programmazione di alto livello. Sulla base del metacoding verrà anche proposto un flusso di design automatico in grado di semplificare la progettazione e la configurazione di una NoC da parte del designer di rete. Come anticipato, la discussione si sposterà poi a livello di sistema, per affrontare la progettazione di tali sistemi dal punto di vista applicativo, focalizzando l'attenzione in particolare sulle applicazioni di monitoraggio remoto. A tal riguardo saranno studiati nel dettaglio tutti gli aspetti che riguardano la progettazione di un sistema per il monitoraggio di pazienti affetti da scompenso cardiaco cronico. Si partirà dalla definizione dei requisiti, che, come spesso accade a questo livello, derivano principalmente dai bisogni dell'utente finale, nel nostro caso medici e pazienti. Verranno discusse le problematiche di acquisizione, elaborazione e gestione delle misure. Il sistema proposto introduce vari aspetti innovativi tra i quali il concetto di protocollo operativo e l'elevata interoperabilità offerta. In ultima analisi, verranno riportati i risultati relativi alla sperimentazione del sistema implementato. Infine, il tema del monitoraggio remoto sarà concluso con lo studio delle reti di distribuzione elettrica intelligenti: le Smart Grid, cercando di fare uno studio dello stato dell'arte del settore, proponendo un'architettura di Home Area Network (HAN) e suggerendone una possibile implementazione attraverso Commercial Off the Shelf (COTS)

Emerging Converter Topologies and Control for Grid Connected Photovoltaic Systems

Continuous cost reduction of photovoltaic (PV) systems and the rise of power auctions resulted in the establishment of PV power not only as a green energy source but also as a cost-effective solution to the electricity generation market. Various commercial solutions for grid-connected PV systems are available at any power level, ranging from multi-megawatt utility-scale solar farms to sub-kilowatt residential PV installations. Compared to utility-scale systems, the feasibility of small-scale residential PV installations is still limited by existing technologies that have not yet properly address issues like operation in weak grids, opaque and partial shading, etc. New market drivers such as warranty improvement to match the PV module lifespan, operation voltage range extension for application flexibility, and embedded energy storage for load shifting have again put small-scale PV systems in the spotlight. This Special Issue collects the latest developments in the field of power electronic converter topologies, control, design, and optimization for better energy yield, power conversion efficiency, reliability, and longer lifetime of the small-scale PV systems. This Special Issue will serve as a reference and update for academics, researchers, and practicing engineers to inspire new research and developments that pave the way for next-generation PV systems for residential and small commercial applications

Principles, fundamentals, and applications of programmable integrated photonics

[EN] Programmable integrated photonics is an emerging new paradigm that aims at designing common integrated optical hardware resource configurations, capable of implementing an unconstrained variety of functionalities by suitable programming, following a parallel but not identical path to that of integrated electronics in the past two decades of the last century. Programmable integrated photonics is raising considerable interest, as it is driven by the surge of a considerable number of new applications in the fields of telecommunications, quantum information processing, sensing, and neurophotonics, calling for flexible, reconfigurable, low-cost, compact, and low-power-consuming devices that can cooperate with integrated electronic devices to overcome the limitation expected by the demise of Moore¿s Law. Integrated photonic devices exploiting full programmability are expected to scale from application-specific photonic chips (featuring a relatively low number of functionalities) up to very complex application-agnostic complex subsystems much in the same way as field programmable gate arrays and microprocessors operate in electronics. Two main differences need to be considered. First, as opposed to integrated electronics, programmable integrated photonics will carry analog operations over the signals to be processed. Second, the scale of integration density will be several orders of magnitude smaller due to the physical limitations imposed by the wavelength ratio of electrons and light wave photons. The success of programmable integrated photonics will depend on leveraging the properties of integrated photonic devices and, in particular, on research into suitable interconnection hardware architectures that can offer a very high spatial regularity as well as the possibility of independently setting (with a very low power consumption) the interconnection state of each connecting element. Integrated multiport interferometers and waveguide meshes provide regular and periodic geometries, formed by replicating unit elements and cells, respectively. In the case of waveguide meshes, the cells can take the form of a square, hexagon, or triangle, among other configurations. Each side of the cell is formed by two integrated waveguides connected by means of a Mach¿Zehnder interferometer or a tunable directional coupler that can be operated by means of an output control signal as a crossbar switch or as a variable coupler with independent power division ratio and phase shift. In this paper, we provide the basic foundations and principles behind the construction of these complex programmable circuits. We also review some practical aspects that limit the programming and scalability of programmable integrated photonics and provide an overview of some of the most salient applications demonstrated so far.European Research Council; Conselleria d'Educació, Investigació, Cultura i Esport; Ministerio de Ciencia, Innovación y Universidades; European Cooperation in Science and Technology; Horizon 2020 Framework Programme.Pérez-López, D.; Gasulla Mestre, I.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Principles, fundamentals, and applications of programmable integrated photonics. Advances in Optics and Photonics. 12(3):709-786. https://doi.org/10.1364/AOP.387155709786123Lyke, J. C., Christodoulou, C. G., Vera, G. A., & Edwards, A. H. (2015). An Introduction to Reconfigurable Systems. Proceedings of the IEEE, 103(3), 291-317. doi:10.1109/jproc.2015.2397832Kaeslin, H. (2008). Digital Integrated Circuit Design. doi:10.1017/cbo9780511805172Trimberger, S. M. (2015). Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology. Proceedings of the IEEE, 103(3), 318-331. doi:10.1109/jproc.2015.2392104Mitola, J. (1995). The software radio architecture. IEEE Communications Magazine, 33(5), 26-38. doi:10.1109/35.393001Nunes, B. A. A., Mendonca, M., Nguyen, X.-N., Obraczka, K., & Turletti, T. (2014). A Survey of Software-Defined Networking: Past, Present, and Future of Programmable Networks. IEEE Communications Surveys & Tutorials, 16(3), 1617-1634. doi:10.1109/surv.2014.012214.00180Papagianni, C., Leivadeas, A., Papavassiliou, S., Maglaris, V., Cervello-Pastor, C., & Monje, A. (2013). On the optimal allocation of virtual resources in cloud computing networks. IEEE Transactions on Computers, 62(6), 1060-1071. doi:10.1109/tc.2013.31Peruzzo, A., Laing, A., Politi, A., Rudolph, T., & O’Brien, J. L. (2011). Multimode quantum interference of photons in multiport integrated devices. Nature Communications, 2(1). doi:10.1038/ncomms1228Metcalf, B. J., Thomas-Peter, N., Spring, J. B., Kundys, D., Broome, M. A., Humphreys, P. C., … Walmsley, I. A. (2013). Multiphoton quantum interference in a multiport integrated photonic device. Nature Communications, 4(1). doi:10.1038/ncomms2349Miller, D. A. B. (2013). Self-aligning universal beam coupler. Optics Express, 21(5), 6360. doi:10.1364/oe.21.006360Miller, D. A. B. (2013). Self-configuring universal linear optical component [Invited]. Photonics Research, 1(1), 1. doi:10.1364/prj.1.000001Carolan, J., Harrold, C., Sparrow, C., Martín-López, E., Russell, N. J., Silverstone, J. W., … Laing, A. (2015). Universal linear optics. Science, 349(6249), 711-716. doi:10.1126/science.aab3642Harris, N. C., Steinbrecher, G. R., Prabhu, M., Lahini, Y., Mower, J., Bunandar, D., … Englund, D. (2017). Quantum transport simulations in a programmable nanophotonic processor. Nature Photonics, 11(7), 447-452. doi:10.1038/nphoton.2017.95Birth of the programmable optical chip. (2015). Nature Photonics, 10(1), 1-1. doi:10.1038/nphoton.2015.265Zhuang, L., Roeloffzen, C. G. H., Hoekman, M., Boller, K.-J., & Lowery, A. J. (2015). Programmable photonic signal processor chip for radiofrequency applications. Optica, 2(10), 854. doi:10.1364/optica.2.000854Pérez, D., Gasulla, I., Capmany, J., & Soref, R. A. (2016). Reconfigurable lattice mesh designs for programmable photonic processors. Optics Express, 24(11), 12093. doi:10.1364/oe.24.012093Capmany, J., Gasulla, I., & Pérez, D. (2015). The programmable processor. Nature Photonics, 10(1), 6-8. doi:10.1038/nphoton.2015.254Pérez, D., Gasulla, I., Crudgington, L., Thomson, D. J., Khokhar, A. Z., Li, K., … Capmany, J. (2017). Multipurpose silicon photonics signal processor core. Nature Communications, 8(1). doi:10.1038/s41467-017-00714-1Clements, W. R., Humphreys, P. C., Metcalf, B. J., Kolthammer, W. S., & Walsmley, I. A. (2016). Optimal design for universal multiport interferometers. Optica, 3(12), 1460. doi:10.1364/optica.3.001460Perez, D., Gasulla, I., Fraile, F. J., Crudgington, L., Thomson, D. J., Khokhar, A. Z., … Capmany, J. (2017). Silicon Photonics Rectangular Universal Interferometer. Laser & Photonics Reviews, 11(6), 1700219. doi:10.1002/lpor.201700219Shen, Y., Harris, N. C., Skirlo, S., Prabhu, M., Baehr-Jones, T., Hochberg, M., … Soljačić, M. (2017). Deep learning with coherent nanophotonic circuits. Nature Photonics, 11(7), 441-446. doi:10.1038/nphoton.2017.93Ribeiro, A., Ruocco, A., Vanacker, L., & Bogaerts, W. (2016). Demonstration of a 4 × 4-port universal linear circuit. Optica, 3(12), 1348. doi:10.1364/optica.3.001348Annoni, A., Guglielmi, E., Carminati, M., Ferrari, G., Sampietro, M., Miller, D. A., … Morichetti, F. (2017). Unscrambling light—automatically undoing strong mixing between modes. Light: Science & Applications, 6(12), e17110-e17110. doi:10.1038/lsa.2017.110Perez, D., Gasulla, I., & Capmany, J. (2018). Toward Programmable Microwave Photonics Processors. Journal of Lightwave Technology, 36(2), 519-532. doi:10.1109/jlt.2017.2778741Chen, L., Hall, E., Theogarajan, L., & Bowers, J. (2011). Photonic Switching for Data Center Applications. IEEE Photonics Journal, 3(5), 834-844. doi:10.1109/jphot.2011.2166994Miller, D. A. B. (2017). Meshing optics with applications. Nature Photonics, 11(7), 403-404. doi:10.1038/nphoton.2017.104Thomas-Peter, N., Langford, N. K., Datta, A., Zhang, L., Smith, B. J., Spring, J. B., … Walmsley, I. A. (2011). Integrated photonic sensing. New Journal of Physics, 13(5), 055024. doi:10.1088/1367-2630/13/5/055024Smit, M., Leijtens, X., Ambrosius, H., Bente, E., van der Tol, J., Smalbrugge, B., … van Veldhoven, R. (2014). An introduction to InP-based generic integration technology. Semiconductor Science and Technology, 29(8), 083001. doi:10.1088/0268-1242/29/8/083001Coldren, L. A., Nicholes, S. C., Johansson, L., Ristic, S., Guzzon, R. S., Norberg, E. J., & Krishnamachari, U. (2011). High Performance InP-Based Photonic ICs—A Tutorial. Journal of Lightwave Technology, 29(4), 554-570. doi:10.1109/jlt.2010.2100807Kish, F., Nagarajan, R., Welch, D., Evans, P., Rossi, J., Pleumeekers, J., … Joyner, C. (2013). From Visible Light-Emitting Diodes to Large-Scale III–V Photonic Integrated Circuits. Proceedings of the IEEE, 101(10), 2255-2270. doi:10.1109/jproc.2013.2275018Hochberg, M., & Baehr-Jones, T. (2010). Towards fabless silicon photonics. Nature Photonics, 4(8), 492-494. doi:10.1038/nphoton.2010.172Bogaerts, W., Fiers, M., & Dumon, P. (2014). Design Challenges in Silicon Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 20(4), 1-8. doi:10.1109/jstqe.2013.2295882Soref, R. (2006). The Past, Present, and Future of Silicon Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 12(6), 1678-1687. doi:10.1109/jstqe.2006.883151Chrostowski, L., & Hochberg, M. (2015). Silicon Photonics Design. doi:10.1017/cbo9781316084168Heck, M. J. R., Bauters, J. F., Davenport, M. L., Doylend, J. K., Jain, S., Kurczveil, G., … Bowers, J. E. (2013). Hybrid Silicon Photonic Integrated Circuit Technology. IEEE Journal of Selected Topics in Quantum Electronics, 19(4), 6100117-6100117. doi:10.1109/jstqe.2012.2235413Keyvaninia, S., Muneeb, M., Stanković, S., Van Veldhoven, P. J., Van Thourhout, D., & Roelkens, G. (2012). Ultra-thin DVS-BCB adhesive bonding of III-V wafers, dies and multiple dies to a patterned silicon-on-insulator substrate. Optical Materials Express, 3(1), 35. doi:10.1364/ome.3.000035Heideman, R., Hoekman, M., & Schreuder, E. (2012). TriPleX-Based Integrated Optical Ring Resonators for Lab-on-a-Chip and Environmental Detection. IEEE Journal of Selected Topics in Quantum Electronics, 18(5), 1583-1596. doi:10.1109/jstqe.2012.2188382Roeloffzen, C. G. H., Zhuang, L., Taddei, C., Leinse, A., Heideman, R. G., van Dijk, P. W. L., … Boller, K.-J. (2013). Silicon nitride microwave photonic circuits. Optics Express, 21(19), 22937. doi:10.1364/oe.21.022937Corbett, B., Loi, R., Zhou, W., Liu, D., & Ma, Z. (2017). Transfer print techniques for heterogeneous integration of photonic components. Progress in Quantum Electronics, 52, 1-17. doi:10.1016/j.pquantelec.2017.01.001Van der Tol, J. J. G. M., Jiao, Y., Shen, L., Millan-Mejia, A., Pogoretskii, V., van Engelen, J. P., & Smit, M. K. (2018). Indium Phosphide Integrated Photonics in Membranes. IEEE Journal of Selected Topics in Quantum Electronics, 24(1), 1-9. doi:10.1109/jstqe.2017.2772786Bachmann, M., Besse, P. A., & Melchior, H. (1994). General self-imaging properties in N × N multimode interference couplers including phase relations. Applied Optics, 33(18), 3905. doi:10.1364/ao.33.003905Soldano, L. B., & Pennings, E. C. M. (1995). Optical multi-mode interference devices based on self-imaging: principles and applications. Journal of Lightwave Technology, 13(4), 615-627. doi:10.1109/50.372474Madsen, C. K., & Zhao, J. H. (1999). Optical Filter Design and Analysis. Wiley Series in Microwave and Optical Engineering. doi:10.1002/0471213756Desurvire, E. (2009). Classical and Quantum Information Theory. doi:10.1017/cbo9780511803758Knill, E., Laflamme, R., & Milburn, G. J. (2001). A scheme for efficient quantum computation with linear optics. Nature, 409(6816), 46-52. doi:10.1038/35051009Capmany, J., & Pérez, D. (2020). Programmable Integrated Photonics. doi:10.1093/oso/9780198844402.001.0001Spagnolo, N., Vitelli, C., Bentivegna, M., Brod, D. J., Crespi, A., Flamini, F., … Sciarrino, F. (2014). Experimental validation of photonic boson sampling. Nature Photonics, 8(8), 615-620. doi:10.1038/nphoton.2014.135Mennea, P. L., Clements, W. R., Smith, D. H., Gates, J. C., Metcalf, B. J., Bannerman, R. H. S., … Smith, P. G. R. (2018). Modular linear optical circuits. Optica, 5(9), 1087. doi:10.1364/optica.5.001087Perez-Lopez, D., Sanchez, E., & Capmany, J. (2018). Programmable True Time Delay Lines Using Integrated Waveguide Meshes. Journal of Lightwave Technology, 36(19), 4591-4601. doi:10.1109/jlt.2018.2831008Pérez-López, D., Gutierrez, A. M., Sánchez, E., DasMahapatra, P., & Capmany, J. (2019). Integrated photonic tunable basic units using dual-drive directional couplers. Optics Express, 27(26), 38071. doi:10.1364/oe.27.038071Jinguji, K., & Kawachi, M. (1995). Synthesis of coherent two-port lattice-form optical delay-line circuit. Journal of Lightwave Technology, 13(1), 73-82. doi:10.1109/50.350643Mookherjea, S., & Yariv, A. (2002). Coupled resonator optical waveguides. IEEE Journal of Selected Topics in Quantum Electronics, 8(3), 448-456. doi:10.1109/jstqe.2002.1016347Heebner, J. E., Chak, P., Pereira, S., Sipe, J. E., & Boyd, R. W. (2004). Distributed and localized feedback in microresonator sequences for linear and nonlinear optics. Journal of the Optical Society of America B, 21(10), 1818. doi:10.1364/josab.21.001818Fandiño, J. S., Muñoz, P., Doménech, D., & Capmany, J. (2016). A monolithic integrated photonic microwave filter. Nature Photonics, 11(2), 124-129. doi:10.1038/nphoton.2016.233Miller, D. A. B. (2012). All linear optical devices are mode converters. Optics Express, 20(21), 23985. doi:10.1364/oe.20.023985Brown, S. D., Francis, R. J., Rose, J., & Vranesic, Z. G. (1992). Field-Programmable Gate Arrays. doi:10.1007/978-1-4615-3572-0Lee, E. K. F., & Gulak, P. G. (1992). Field programmable analogue array based on MOSFET transconductors. Electronics Letters, 28(1), 28-29. doi:10.1049/el:19920017Lee, E. K. F., & Gulak, P. G. (s. f.). A transconductor-based field-programmable analog array. Proceedings ISSCC ’95 - International Solid-State Circuits Conference. doi:10.1109/isscc.1995.535521Pérez, D., Gasulla, I., & Capmany, J. (2018). Field-programmable photonic arrays. Optics Express, 26(21), 27265. doi:10.1364/oe.26.027265Zheng, D., Doménech, J. D., Pan, W., Zou, X., Yan, L., & Pérez, D. (2019). Low-loss broadband 5  ×  5 non-blocking Si3N4 optical switch matrix. Optics Letters, 44(11), 2629. doi:10.1364/ol.44.002629Densmore, A., Janz, S., Ma, R., Schmid, J. H., Xu, D.-X., Delâge, A., … Cheben, P. (2009). Compact and low power thermo-optic switch using folded silicon waveguides. Optics Express, 17(13), 10457. doi:10.1364/oe.17.010457Song, M., Long, C. M., Wu, R., Seo, D., Leaird, D. E., & Weiner, A. M. (2011). Reconfigurable and Tunable Flat-Top Microwave Photonic Filters Utilizing Optical Frequency Combs. IEEE Photonics Technology Letters, 23(21), 1618-1620. doi:10.1109/lpt.2011.2165209Rudé, M., Pello, J., Simpson, R. E., Osmond, J., Roelkens, G., van der Tol, J. J. G. M., & Pruneri, V. (2013). Optical switching at 1.55 μm in silicon racetrack resonators using phase change materials. Applied Physics Letters, 103(14), 141119. doi:10.1063/1.4824714Zheng, J., Khanolkar, A., Xu, P., Colburn, S., Deshmukh, S., Myers, J., … Majumdar, A. (2018). GST-on-silicon hybrid nanophotonic integrated circuits: a non-volatile quasi-continuously reprogrammable platform. Optical Materials Express, 8(6), 1551. doi:10.1364/ome.8.001551Edinger, P., Errando-Herranz, C., & Gylfason, K. B. (2019). Low-Loss MEMS Phase Shifter for Large Scale Reconfigurable Silicon Photonics. 2019 IEEE 32nd International Conference on Micro Electro Mechanical Systems (MEMS). doi:10.1109/memsys.2019.8870616Carroll, L., Lee, J.-S., Scarcella, C., Gradkowski, K., Duperron, M., Lu, H., … O’Brien, P. (2016). Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices. Applied Sciences, 6(12), 426. doi:10.3390/app6120426Bahadori, M., Gazman, A., Janosik, N., Rumley, S., Zhu, Z., Polster, R., … Bergman, K. (2018). Thermal Rectification of Integrated Microheaters for Microring Resonators in Silicon Photonics Platform. Journal of Lightwave Technology, 36(3), 773-788. doi:10.1109/jlt.2017.2781131Cocorullo, G., Della Corte, F. G., Rendina, I., & Sarro, P. M. (1998). Thermo-optic effect exploitation in silicon microstructures. Sensors and Actuators A: Physical, 71(1-2), 19-26. doi:10.1016/s0924-4247(98)00168-xZecevic, N., Hofbauer, M., & Zimmermann, H. (2015). Integrated Pulsewidth Modulation Control for a Scalable Optical Switch Matrix. IEEE Photonics Journal, 7(6), 1-7. doi:10.1109/jphot.2015.2506153Seok, T. J., Quack, N., Han, S., & Wu, M. C. (2015). 50×50 Digital Silicon Photonic Switches with MEMS-Actuated Adiabatic Couplers. Optical Fiber Communication Conference. doi:10.1364/ofc.2015.m2b.4Zortman, W. A., Trotter, D. C., & Watts, M. R. (2010). Silicon photonics manufacturing. Optics Express, 18(23), 23598. doi:10.1364/oe.18.023598Mower, J., Harris, N. C., Steinbrecher, G. R., Lahini, Y., & Englund, D. (2015). High-fidelity quantum state evolution in imperfect photonic integrated circuits. Physical Review A, 92(3). doi:10.1103/physreva.92.032322Pérez, D., & Capmany, J. (2019). Scalable analysis for arbitrary photonic integrated waveguide meshes. Optica, 6(1), 19. doi:10.1364/optica.6.000019Oton, C. J., Manganelli, C., Bontempi, F., Fournier, M., Fowler, D., & Kopp, C. (2016). Silicon photonic waveguide metrology using Mach-Zehnder interferometers. Optics Express, 24(6), 6265. doi:10.1364/oe.24.006265Chen, X., & Bogaerts, W. (2019). A Graph-based Design and Programming Strategy for Reconfigurable Photonic Circuits. 2019 IEEE Photonics Society Summer Topical Meeting Series (SUM). doi:10.1109/phosst.2019.8795068Zibar, D., Wymeersch, H., & Lyubomirsky, I. (2017). Machine learning under the spotlight. Nature Photonics, 11(12), 749-751. doi:10.1038/s41566-017-0058-3Lopez, D. P. (2020). Programmable Integrated Silicon Photonics Waveguide Meshes: Optimized Designs and Control Algorithms. IEEE Journal of Selected Topics in Quantum Electronics, 26(2), 1-12. doi:10.1109/jstqe.2019.2948048Harris, N. C., Bunandar, D., Pant, M., Steinbrecher, G. R., Mower, J., Prabhu, M., … Englund, D. (2016). Large-scale quantum photonic circuits in silicon. Nanophotonics, 5(3), 456-468. doi:10.1515/nanoph-2015-0146Spring, J. B., Metcalf, B. J., Humphreys, P. C., Kolthammer, W. S., Jin, X.-M., Barbieri, M., … Walmsley, I. A. (2012). Boson Sampling on a Photonic Chip. Science, 339(6121), 798-801. doi:10.1126/science.1231692O’Brien, J. L., Furusawa, A., & Vučković, J. (2009). Photonic quantum technologies. Nature Photonics, 3(12), 687-695. doi:10.1038/nphoton.2009.229Kok, P., Munro, W. J., Nemoto, K., Ralph, T. C., Dowling, J. P., & Milburn, G. J. (2007). Linear optical quantum computing with photonic qubits. Reviews of Modern Physics, 79(1), 135-174. doi:10.1103/revmodphys.79.135Politi, A., Cryan, M. J., Rarity, J. G., Yu, S., & O’Brien, J. L. (2008). Silica-on-Silicon Waveguide Quantum Circuits. Science, 320(5876), 646-649. doi:10.1126/science.1155441Politi, A., Matthews, J., Thompson, M. G., & O’Brien, J. L. (2009). Integrated Quantum Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 15(6), 1673-1684. doi:10.1109/jstqe.2009.2026060Thompson, M. G., Politi, A., Matthews, J. C. F., & O’Brien, J. L. (2011). Integrated waveguide circuits for optical quantum computing. IET Circuits, Devices & Systems, 5(2), 94. doi:10.1049/iet-cds.2010.0108Silverstone, J. W., Bonneau, D., O’Brien, J. L., & Thompson, M. G. (2016). Silicon Quantum Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 22(6), 390-402. doi:10.1109/jstqe.2016.2573218Poot, M., Schuck, C., Ma, X., Guo, X., & Tang, H. X. (2016). Design and characterization of integrated components for SiN photonic quantum circuits. Optics Express, 24(7), 6843. doi:10.1364/oe.24.006843Saleh, M. F., Di Giuseppe, G., Saleh, B. E. A., & Teich, M. C. (2010). Modal and polarization qubits in Ti:LiNbO_3 photonic circuits for a universal quantum logic gate. Optics Express, 18(19), 20475. doi:10.1364/oe.18.020475Harris, N. C., Carolan, J., Bunandar, D., Prabhu, M., Hochberg, M., Baehr-Jones, T., … Englund, D. (2018). Linear programmable nanophotonic processors. Optica, 5(12), 1623. doi:10.1364/optica.5.001623Qiang, X., Zhou, X., Wang, J., Wilkes, C. M., Loke, T., O’Gara, S., … Matthews, J. C. F. (2018). Large-scale silicon quantum photonics implementing arbitrary two-qubit processing. Nature Photonics, 12(9), 534-539. doi:10.1038/s41566-018-0236-yLee, B. G., & Dupuis, N. (2019). Silicon Photonic Switch Fabrics: Technology and Architecture. Journal of Lightwave Technology, 37(1), 6-20. doi:10.1109/jlt.2018.2876828Cheng, Q., Rumley, S., Bahadori, M., & Bergman, K. (2018). Photonic switching in high performance datacenters [Invited]. Optics Express, 26(12), 16022. doi:10.1364/oe.26.016022Wonfor, A., Wang, H., Penty, R. V., & White, I. H. (2011). Large Port Count High-Speed Optical Switch Fabric for Use Within Datacenters [Invited]. Journal of Optical Communications and Networking, 3(8), A32. doi:10.1364/jocn.3.000a32Hamamoto, K., Anan, T., Komatsu, K., Sugimoto, M., & Mito, I. (1992). First 8×8 semiconductor optical matrix switches using GaAs/AlGaAs electro-optic guided-wave directional couplers. Electronics Letters, 28(5), 441. doi:10.1049/el:19920278Van Campenhout, J., Green, W. M., Assefa, S., & Vlasov, Y. A. (2009). Low-power, 2×2 silicon electro-optic switch with 110-nm bandwidth for broadband reconfigurable optical networks. Optics Express, 17(26), 24020. doi:10.1364/oe.17.024020Dupuis, N., Lee, B. G., Rylyakov, A. V., Kuchta, D. M., Baks, C. W., Orcutt, J. S., … Schow, C. L. (2015). D