Modellierung und automatische Generierung von FPGA-basierten Testinstrumenten für den strukturellen Leiterplattentest

Neue Bauformen von Schaltkreisen wie BGAs führen zu sinkenden Möglichkeiten des optischen und mechanischen Testzugriffs und stellen Testsysteme vor Probleme bei der Testbarkeit von Verbindungen zwischen ICs auf Leiterplatten. Damit verbunden sind eine reduzierte Testabdeckung und steigende Kosten. Besonders für FPGAs fehlen geeignete Methoden, bei denen sich das Testsystem automatisch den Gegebenheiten der zu testenden Leiterplatte anpasst. Diese Dissertation beschäftigt sich mit dem Problem des FPGA-basierten Testens. Das vorgestellte Konzept nutzt ausschließlich vorhandene Ressourcen des FPGAs, um Testalgorithmen in dessen Logik zu implementieren und erhöht die Herstellungskosten der Leiterplatte nicht. Die Ressourcen des FPGAs stehen während der Testphase exklusiv für das Testen zur Verfügung. Ausgehend vom Stand der Technik nicht-invasiver elektrischer Verfahren für Leiterplattentests werden aktuelle Ansätze und Methoden miteinander verglichen. Aus deren Stärken und Schwächen wird eine detaillierte Zielstellung für diese Dissertation erarbeitet. Es wird eine Methode zur Generierung von Testinstrumenten für das FPGA-basierte Testen vorgestellt, die die Ausführung von Testalgorithmen in den FPGA verlagern und eine vergleichbare oder bessere Testabdeckung sowie Testgeschwindigkeit als etablierte Verfahren liefert, ohne dafür auf manuelle Eingriffe bei der Generierung angewiesen zu sein. Im Rahmen eines Lösungsansatzes wird neben der Testsystemarchitektur eine Modellierung für die an den Verbindungstests beteiligten Schaltkreise vorgestellt. Hierbei wird die Ausführung der Testalgorithmen im FPGA entweder in Software auf einem softcore-basierten Prozessor oder direkt in Hardware als diskrete Logik in einem sogenannten Co-Prozessor ermöglicht. Mit der Methode ist es möglich jeden Schaltkreis getrennt und unabhängig von der Art seiner späteren Implementierung und den konkreten Gegebenheiten des Prüflings zu modellieren. Die Generierung aller nötigen Bestandteile in Software und Hardware, wie auch deren Integration zu einem Testinstrument erfolgen dabei vollständig automatisch. Kern der Arbeit ist die Modellierung und Generierung für eingebettete Testinstrumente, die auf der Testsystemarchitektur basieren. Der Fokus wird dabei auf die zeitlich korrekte Ansteuerung der an den Verbindungstests beteiligten Schaltkreise gelegt, ohne dabei eine konkrete Implementierung vorzugeben. In Untersuchungen wird die Generierung von Testinstrumenten für verschiedene Schaltkreise betrachtet. Die Ergebnisse belegen die Leistungsfähigkeit der vorgestellten Methode zur automatischen Generierung von FPGA-basierten Testinstrumenten und zeigen eine signifikante Beschleunigung des FPGA-basierten Verbindungstests.New types of cases for integrated circuits like BGAs are leading to a decreased optical and mechanical test access. They are causing problems for test systems when testing connections between integrated circuits on printed circuit boards. This causes decreasing test coverage and increasing test costs. Especially for FPGAs some appropriate methods that automatically adapt the test system to the conditions of the printed circuit board are missing. This thesis is about the problems of FPGA-based testing. The presented concept solely uses available resources of the FPGA to transfer test algorithms from external test equipment into the programmable logic of the FPGA and therefore does not increase the production costs of the printed circuit board. The resources of the FPGA are exclusively used for testing during the test phase. Based on state-of-the-art non-invasive electrical methods for printed circuit boards with FPGAs current approaches are compared and analyzed. From the strengths and weaknesses of the considered methods a detailed description of the goals that should be achieved with this thesis is discussed. A method for the generation of so called test instruments for FPGA-based testing is presented. This method transfers the execution of test algorithms into the FPGA and has a similar or better test coverage as well as test speed compared to the well-established techniques without the need for any manually actions when generating such systems. Besides the chosen test system architecture the modeling of integrated circuits that are part of the connection test is presented. The test system architecture allows the execution of test algorithms either in software on a soft-core processor or directly in dedicated logic, so called co-processors. With this method it is possible to model each integrated circuit independent of each other and also independent of the implementation in software or hardware. The generation of all software and hardware parts of the test system is done fully automatically. Central element of this thesis is the modeling and generation of embedded test instruments, based on the presented test system architecture. The focus is on the timing-correct control routines of the integrated circuits that are part of the connection test. All parts of the test system should be modeled independent of each other and without knowledge about the use case. In experiments the generation of test instruments for different integrated circuits is carried out. These experiments prove the performance of the proposed methods for automatic generation of FPGA-based test instrument and show a significant speed-up for FPGA-based tests of printed circuit boards

Towards an embedded board-level tester: study of a configurable test processor

The demand for electronic systems with more features, higher performance, and less power consumption increases continuously. This is a real challenge for design and test engineers because they have to deal with electronic systems with ever-increasing complexity maintaining production and test costs low and meeting critical time to market deadlines. For a test engineer working at the board-level, this means that manufacturing defects must be detected as soon as possible and at a low cost. However, the use of classical test techniques for testing modern printed circuit boards is not sufficient, and in the worst case these techniques cannot be used at all. This is mainly due to modern packaging technologies, a high device density, and high operation frequencies of modern printed circuit boards. This leads to very long test times, low fault coverage, and high test costs. This dissertation addresses these issues and proposes an FPGA-based test approach for printed circuit boards. The concept is based on a configurable test processor that is temporarily implemented in the on-board FPGA and provides the corresponding mechanisms to communicate to external test equipment and co-processors implemented in the FPGA. This embedded test approach provides the flexibility to implement test functions either in the external test equipment or in the FPGA. In this manner, tests are executed at-speed increasing the fault coverage, test times are reduced, and the test system can be adapted automatically to the properties of the FPGA and devices located on the board. An essential part of the FPGA-based test approach deals with the development of a test processor. In this dissertation the required properties of the processor are discussed, and it is shown that the adaptation to the specific test scenario plays a very important role for the optimization. For this purpose, the test processor is equipped with configuration parameters at the instruction set architecture and microarchitecture level. Additionally, an automatic generation process for the test system and for the computation of some of the processor’s configuration parameters is proposed. The automatic generation process uses as input a model known as the device under test model (DUT-M). In order to evaluate the entire FPGA-based test approach and the viability of a processor for testing printed circuit boards, the developed test system is used to test interconnections to two different devices: a static random memory (SRAM) and a liquid crystal display (LCD). Experiments were conducted in order to determine the resource utilization of the processor and FPGA-based test system and to measure test time when different test functions are implemented in the external test equipment or the FPGA. It has been shown that the introduced approach is suitable to test printed circuit boards and that the test processor represents a realistic alternative for testing at board-level.Der Bedarf an elektronischen Systemen mit zusätzlichen Merkmalen, höherer Leistung und geringerem Energieverbrauch nimmt ständig zu. Dies stellt eine erhebliche Herausforderung für Entwicklungs- und Testingenieure dar, weil sie sich mit elektronischen Systemen mit einer steigenden Komplexität zu befassen haben. Außerdem müssen die Herstellungs- und Testkosten gering bleiben und die Produkteinführungsfristen so kurz wie möglich gehalten werden. Daraus folgt, dass ein Testingenieur, der auf Leiterplatten-Ebene arbeitet, die Herstellungsfehler so früh wie möglich entdecken und dabei möglichst niedrige Kosten verursachen soll. Allerdings sind die klassischen Testmethoden nicht in der Lage, die Anforderungen von modernen Leiterplatten zu erfüllen und im schlimmsten Fall können diese Testmethoden überhaupt nicht verwendet werden. Dies liegt vor allem an modernen Gehäuse-Technologien, der hohen Bauteildichte und den hohen Arbeitsfrequenzen von modernen Leiterplatten. Das führt zu sehr langen Testzeiten, geringer Testabdeckung und hohen Testkosten. Die Dissertation greift diese Problematik auf und liefert einen FPGA-basierten Testansatz für Leiterplatten. Das Konzept beruht auf einem konfigurierbaren Testprozessor, welcher im On-Board-FPGA temporär implementiert wird und die entsprechenden Mechanismen für die Kommunikation mit der externen Testeinrichtung und Co-Prozessoren im FPGA bereitstellt. Dadurch ist es möglich Testfunktionen flexibel entweder auf der externen Testeinrichtung oder auf dem FPGA zu implementieren. Auf diese Weise werden Tests at-speed ausgeführt, um die Testabdeckung zu erhöhen. Außerdem wird die Testzeit verkürzt und das Testsystem automatisch an die Eigenschaften des FPGAs und anderer Bauteile auf der Leiterplatte angepasst. Ein wesentlicher Teil des FPGA-basierten Testansatzes umfasst die Entwicklung eines Testprozessors. In dieser Dissertation wird über die benötigten Eigenschaften des Prozessors diskutiert und es wird gezeigt, dass die Anpassung des Prozessors an den spezifischen Testfall von großer Bedeutung für die Optimierung ist. Zu diesem Zweck wird der Prozessor mit Konfigurationsparametern auf der Befehlssatzarchitektur-Ebene und Mikroarchitektur-Ebene ausgerüstet. Außerdem wird ein automatischer Generierungsprozess für die Realisierung des Testsystems und für die Berechnung einer Untergruppe von Konfigurationsparametern des Prozessors vorgestellt. Der automatische Generierungsprozess benutzt als Eingangsinformation ein Modell des Prüflings (device under test model, DUT-M). Das entwickelte Testsystem wurde zum Testen von Leiterplatten für Verbindungen zwischen dem FPGA und zwei Bauteilen verwendet, um den FPGA-basierten Testansatz und die Durchführbarkeit des Testprozessors für das Testen auf Leiterplatte-Ebene zu evaluieren. Die zwei Bauteile sind ein Speicher mit direktem Zugriff (static random-access memory, SRAM) und eine Flüssigkristallanzeige (liquid crystal display, LCD). Die Experimente wurden durchgeführt, um den Ressourcenverbrauch des Prozessors und Testsystems festzustellen und um die Testzeit zu messen. Dies geschah durch die Implementierung von unterschiedlichen Testfunktionen auf der externen Testeinrichtung und dem FPGA. Dadurch konnte gezeigt werden, dass der FPGA-basierte Ansatz für das Testen von Leiterplatten geeignet ist und dass der Testprozessor eine realistische Alternative für das Testen auf Leiterplatten-Ebene ist

DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

Time-efficient fault detection and diagnosis system for analog circuits

Time-efficient fault analysis and diagnosis of analog circuits are the most important prerequisites to achieve online health monitoring of electronic equipments, which are involving continuing challenges of ultra-large-scale integration, component tolerance, limited test points but multiple faults. This work reports an FPGA (field programmable gate array)-based analog fault diagnostic system by applying two-dimensional information fusion, two-port network analysis and interval math theory. The proposed system has three advantages over traditional ones. First, it possesses high processing speed and smart circuit size as the embedded algorithms execute parallel on FPGA. Second, the hardware structure has a good compatibility with other diagnostic algorithms. Third, the equipped Ethernet interface enhances its flexibility for remote monitoring and controlling. The experimental results obtained from two realistic example circuits indicate that the proposed methodology had yielded competitive performance in both diagnosis accuracy and time-effectiveness, with about 96% accuracy while within 60 ms computational time.Peer reviewedFinal Published versio

Printed Circuit Board (PCB) design process and fabrication

This module describes main characteristics of Printed Circuit Boards (PCBs). A brief history of PCBs is introduced in the first chapter. Then, the design processes and the fabrication of PCBs are addressed and finally a study case is presented in the last chapter of the module.Peer ReviewedPostprint (published version

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Fault Tolerant Electronic System Design

Due to technology scaling, which means reduced transistor size, higher density, lower voltage and more aggressive clock frequency, VLSI devices may become more sensitive against soft errors. Especially for those devices used in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena (e.g., aging and wear-out effects) also have negative impacts on reliability of modern circuits. Recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems. On one hand, processor-based system are commonly used in a wide variety of applications, including safety-critical and high availability missions, e.g., in the automotive, biomedical and aerospace domains. In these fields, an error may produce catastrophic consequences. Thus, dependability is a primary target that must be achieved taking into account tight constraints in terms of cost, performance, power and time to market. With standards and regulations (e.g., ISO-26262, DO-254, IEC-61508) clearly specify the targets to be achieved and the methods to prove their achievement, techniques working at system level are particularly attracting. On the other hand, Field Programmable Gate Array (FPGA) devices are becoming more and more attractive, also in safety- and mission-critical applications due to the high performance, low power consumption and the flexibility for reconfiguration they provide. Two types of FPGAs are commonly used, based on their configuration memory cell technology, i.e., SRAM-based and Flash-based FPGA. For SRAM-based FPGAs, the SRAM cells of the configuration memory highly susceptible to radiation induced effects which can leads to system failure; and for Flash-based FPGAs, even though their non-volatile configuration memory cells are almost immune to Single Event Upsets induced by energetic particles, the floating gate switches and the logic cells in the configuration tiles can still suffer from Single Event Effects when hit by an highly charged particle. So analysis and mitigation techniques for Single Event Effects on FPGAs are becoming increasingly important in the design flow especially when reliability is one of the main requirements

Development of a TIM-compliant TMS320C6x DSP module

The development of a Texas instruments Module (TIM) compliant Digital SignalProcessor (DSP) module, using the Texas Instruments TMS320C6201 (C6201) DSP, is presented. Currently, DSP modules based on the Texas Instruments TMS320C4x(C4x) family of DSPs are widely used for message passing multiprocessing DSPapplications such as real-time processing of data and image processing. The Interconnection of the TIM-compliant C4x DSP modules is accomplished using motherboards based on standard bus types, such as VME or PCI, and communication ports (comm ports) built into the C4x DSP. The purpose of the work described in this thesis was to provide a TIM-compliant DSP module with the improved computational performance of the C6x family of DSPs, which would also be compatible with theexisting VME or PCI bus motherboards.One drawback to using the C6201 DSPs in this application is the lack of C4xtype communication ports (comm ports) in these new DSPs. In order for the C6201 TIM to be compatible with the existing motherboards, it must provide C4x- compatible commport functionality. An FPGA was used to convert the C6x host port into multiple C4x compatible communication ports and to provide the potential for future co-processinghardware.The major effort of this development was the designing, building and testing of the C6x module hardware and the C4x-compatible comm port interface implemented in FPGA. The first phase of this design involved the hardware architecture; this consisted of the selection of components needed to fulfill the design constraints, and the design of the module printed circuit board (PCB). The major components of this DSPmodule consist of theC6201 DSP. The external ai memory devices, and an Altera PF10 10pA Field Programmable Gate Array (FPGA). The memory devices include 4MB of SDRAM. 256kB of SBSRAM, and a 512kB Flash ROM for storing boot code. The Second phase of this design dealt with the host port to comm port conversion hardware implemented in the FPGA. The C6x host port was used to exchange data and control information with the FPGA. This hardware was developed in the VHDL hardware description language and graphic design files using Altera MAX+PLUS II software.The C6201 DSP module has been built and tested. The board successfully executed both read and write transfers with another motherboard using the C4x compatible communication port interface. The data exchange was across a 2.5\u27 ribbon cable at an average read transfer data rate of 7.18 Mbytes/S and an average write transfer data rate of 5.15 Mbytes/S