284 research outputs found
A Language and Hardware Independent Approach to Quantum-Classical Computing
Heterogeneous high-performance computing (HPC) systems offer novel
architectures which accelerate specific workloads through judicious use of
specialized coprocessors. A promising architectural approach for future
scientific computations is provided by heterogeneous HPC systems integrating
quantum processing units (QPUs). To this end, we present XACC (eXtreme-scale
ACCelerator) --- a programming model and software framework that enables
quantum acceleration within standard or HPC software workflows. XACC follows a
coprocessor machine model that is independent of the underlying quantum
computing hardware, thereby enabling quantum programs to be defined and
executed on a variety of QPUs types through a unified application programming
interface. Moreover, XACC defines a polymorphic low-level intermediate
representation, and an extensible compiler frontend that enables language
independent quantum programming, thus promoting integration and
interoperability across the quantum programming landscape. In this work we
define the software architecture enabling our hardware and language independent
approach, and demonstrate its usefulness across a range of quantum computing
models through illustrative examples involving the compilation and execution of
gate and annealing-based quantum programs
Advances in Architectures and Tools for FPGAs and their Impact on the Design of Complex Systems for Particle Physics
The continual improvement of semiconductor technology has provided rapid advancements in device frequency and density. Designers of electronics systems for high-energy physics (HEP) have benefited from these advancements, transitioning many designs from fixed-function ASICs to more flexible FPGA-based platforms. Today’s FPGA devices provide a significantly higher amount of resources than those available during the initial Large Hadron Collider design phase. To take advantage of the capabilities of future FPGAs in the next generation of HEP experiments, designers must not only anticipate further improvements in FPGA hardware, but must also adopt design tools and methodologies that can scale along with that hardware. In this paper, we outline the major trends in FPGA hardware, describe the design challenges these trends will present to developers of HEP electronics, and discuss a range of techniques that can be adopted to overcome these challenges
BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox
In this work, we introduce a platform for register-transfer level (RTL)
architecture design space exploration. The platform is an open-source,
parameterized, synthesizable set of RTL modules for designing RISC-V based
single and multi-core architecture systems. The platform is designed with a
high degree of modularity. It provides highly-parameterized, composable RTL
modules for fast and accurate exploration of different RISC-V based core
complexities, multi-level caching and memory organizations, system topologies,
router architectures, and routing schemes. The platform can be used for both
RTL simulation and FPGA based emulation. The hardware modules are implemented
in synthesizable Verilog using no vendor-specific blocks. The platform includes
a RISC-V compiler toolchain to assist in developing software for the cores, a
web-based system configuration graphical user interface (GUI) and a web-based
RISC-V assembly simulator. The platform supports a myriad of RISC-V
architectures, ranging from a simple single cycle processor to a multi-core SoC
with a complex memory hierarchy and a network-on-chip. The modules are designed
to support incremental additions and modifications. The interfaces between
components are particularly designed to allow parts of the processor such as
whole cache modules, cores or individual pipeline stages, to be modified or
replaced without impacting the rest of the system. The platform allows
researchers to quickly instantiate complete working RISC-V multi-core systems
with synthesizable RTL and make targeted modifications to fit their needs. The
complete platform (including Verilog source code) can be downloaded at
https://ascslab.org/research/briscv/explorer/explorer.html.Comment: In Proceedings of the 2019 ACM/SIGDA International Symposium on
Field-Programmable Gate Arrays (FPGA '19
Thermal analysis and modeling of embedded processors
This paper presents a complete modeling approach to analyze the thermal behavior of microprocessor-based systems. While most compact modeling approaches require a deep knowledge of the implementation details, our method defines a black box technique which can be applied to different target processors when this detailed information is unknown. The obtained results show high accuracy, applicability and can be easily automated. The proposed methodology has been used to study the impact of code transformations in the thermal behavior of the chip. Finally, the analysis of the thermal effect of the source code modifications can be included in a temperature-aware compiler which minimizes the total temperature of the chip, as well as the temperature gradients, according to these guidelines
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