Characterizing Behavioural Congruences for Petri Nets

We exploit a notion of interface for Petri nets in order to design a set of net combinators. For such a calculus of nets, we focus on the behavioural congruences arising from four simple notions of behaviour, viz., traces, maximal traces, step, and maximal step traces, and from the corresponding four notions of bisimulation, viz., weak and weak step bisimulation and their maximal versions. We characterize such congruences via universal contexts and via games, providing in such a way an understanding of their discerning powers

Design of an Interlock Module for Use in a Globally Asynchronous, Locally Synchronous Design Methodology

As the number of transistors on a single integrated circuit approach a billion, the problems of clock distribution, power consumption, multiple clock domains, meeting timing requirements, and reuse of subsystem designs grow ever more difficult. Coordinating a billion transistors with the present design methodologies will require hundreds of years of engineering time. A new design methodology is needed. The GALS (Globally Asynchronous Locally Synchronous) approach, that blends clockless and clocked subsystems is a strong contender

Robot control in a message passing environment: theoretical questions and preliminary experiments

The performance of real-time distributed control systems is shown to depend critically on both communication and computation costs. A taxonomy for distributed system performance measurement is introduced. A roughly accurate method of performance prediction for simple systems is presented. Experimental results demonstrate the effects of communication protocols on real-world system performance

Petri Nets and Other Models of Concurrency

This paper retraces, collects, and summarises contributions of the authors --- in collaboration with others --- on the theme of Petri nets and their categorical relationships to other models of concurrency

Liveness of extended control structure nets

Journal ArticleA new subclass of Petri nets is defined allowing the control structure representation of parallel programs including arbitrary semaphore operations. Structural properties of the "Extended Control Structure Nets" are discussed and seven necessary and sufficient conditions for their liveness are proved

Towards a Theory of Universal Speed-Independent Modules

Of concern here are asynchronous modules, i.e., those whose activity is regulated by initiation and completion signals with no clocks being present. First a number of operating conditions are described that are deemed essential or useful in a system of asynchronous modules, while retaining an air of independence of particular hardware implementations as much as possible. Second, some results are presented concerning sets of modules that are universal with respect to these conditions. That is, from these sets any arbitrarily complex module may be constructed as a network. It is stipulated that such constructions be speed independent, i.e., independent of the delay time involved in any constituent modules. Furthermore it is required that the constructions be delay insensitive in the sense that an arbitrary number of delay elements may be inserted into or removed from connecting lines without effecting the external behavior of the network

Graph model analysis of computer structures

Graph theory is applicable to the solving of problems in nearly every field of scientific study. The purpose of this thesis is to consider its applications in representing and analyzing digital computers. Fundamental graph theory definitions, the types and the properties of the directed graphs, the matrix representation, and several reduction techniques are discussed. The blocking gate method for diagnosing computer systems is described and applied to the Scientific Control Corporation (SCC) 650 for its fault-diagnosis. Microprogramming has been a significant trend in hardware and software designs of computers. Microprogrammed computers are discussed in comparison to conventional computers. A general scheme utilizing four nodes generates directed graphs for both types of architecture. The directed graphs are studied with respect to the flexibility and cost parameters --Abstract, page ii