An assertion-based proof system for multithreaded Java

AbstractBesides the features of a class-based object-oriented language, Java integrates concurrency via its thread classes, allowing for a multithreaded flow of control. The concurrency model includes synchronous message passing, dynamic thread creation, shared-variable concurrency via instance variables, and coordination via reentrant synchronization monitors.To reason about safety properties of multithreaded Java programs, we introduce an assertional proof method for a multithreaded sublanguage of Java, covering the mentioned concurrency issues as well as the object-based core of Java. The verification method is formulated in terms of proof-outlines, where the assertions are layered into local ones specifying the behavior of a single instance, and global ones taking care of the connections between objects. We establish the soundness and the relative completeness of the proof system. From an annotated program, a number of verification conditions are generated and handed over to the interactive theorem prover PVS

Multivariant Assertion-based Guidance in Abstract Interpretation

Approximations during program analysis are a necessary evil, as they ensure essential properties, such as soundness and termination of the analysis, but they also imply not always producing useful results. Automatic techniques have been studied to prevent precision loss, typically at the expense of larger resource consumption. In both cases (i.e., when analysis produces inaccurate results and when resource consumption is too high), it is necessary to have some means for users to provide information to guide analysis and thus improve precision and/or performance. We present techniques for supporting within an abstract interpretation framework a rich set of assertions that can deal with multivariance/context-sensitivity, and can handle different run-time semantics for those assertions that cannot be discharged at compile time. We show how the proposed approach can be applied to both improving precision and accelerating analysis. We also provide some formal results on the effects of such assertions on the analysis results.Comment: Pre-proceedings paper presented at the 28th International Symposium on Logic-Based Program Synthesis and Transformation (LOPSTR 2018), Frankfurt am Main, Germany, 4-6 September 2018 (arXiv:1808.03326

Performance and area optimization for reliable FPGA-based shifter design

This thesis addresses the problem of implementing reliable FPGA-based shifters. An FPGA-based design requires optimization between performance and resource utilization, and an effective verification methodology to validate design behavior. The FPGA-based implementation of a large shifter design is restricted by an I/O resource bottleneck. The verification of the design behavior presents a further challenge due to the \u27black-box\u27 nature of FPGAs. To tackle these design challenges, we propose a novel approach to implement FPGA-based shifters. The proposed design alleviates the I/O bottleneck while significantly reducing the logic resources required. This is achieved with a minimal increase in the design delay. The design is seamlessly scalable to a multi-FPGA chip setup to improve performance or to implement larger shifters. It is configured using assertion checkers for efficient design verification. The assertion-based design is further optimized to alleviate the performance degradation caused by the assertion checkers

Optimized Temporal Monitors for SystemC

SystemC is a modeling language built as an extension of C++. Its growing popularity and the increasing complexity of designs have motivated research efforts aimed at the verification of SystemC models using assertion-based verification (ABV), where the designer asserts properties that capture the design intent in a formal language such as PSL or SVA. The model then can be verified against the properties using runtime or formal verification techniques. In this paper we focus on automated generation of runtime monitors from temporal properties. Our focus is on minimizing runtime overhead, rather than monitor size or monitor-generation time. We identify four issues in monitor generation: state minimization, alphabet representation, alphabet minimization, and monitor encoding. We conduct extensive experimentation and identify a combination of settings that offers the best performance in terms of runtime overhead

Auditing Symposium VIII: Proceedings of the 1986 Touche Ross/University of Kansas Symposium on Auditing Problems

Discussant\u27s response to On the economics of product differentiation in auditing / Howard R. Osharow; Unresolved issues in classical audit sample evaluations / Donald R. Nichols, Rajendra P. Srivastava, Bart H. Ward; Discussant\u27s response to Unresolved issues in classical audit sample evaluations / Abraham D. Akresh; Under the spreading chestnut tree, accountants\u27 legal liability -- A historical perspective / Paul J. Ostling; Impact of technological events and trends on audit evidence in the year 2000: Phase I / Gary L. Holstrum, Theodore J. Mock, Robert N. West; Discussant\u27s Response to Impact of technological events and trends on audit evidence in the year 2000: Phase I; Is the second standard of fieldwork necessary / Thomas P. Bintinger; Discussant\u27s response to Is the second standard of fieldwork necessary / Andrew D. Bailey; Interim report on the development of an expert system for the auditor\u27s loan loss evaluation / Kirk P. Kelly, Gary S. Ribar, John J. Willingham; Discussant\u27s response to Interim report on the development of an expert system for the auditor\u27s loan loss evaluation / William F. Messier; Work of the Special Investigations Committee / R. K. (Robert Kuhn) Mautz (1915-2002); Discussant\u27s response to Under the spreading chestnut tree, accountants\u27 legal liability -- A historical perspective / Thomas A. Gavin; Assertion based approach to auditing / Donald A. Leslie; Discussant\u27s response to An assertion-based approach to auditing / William L. Felixhttps://egrove.olemiss.edu/dl_proceedings/1007/thumbnail.jp

Hardware Design and Implementation of Role-Based Cryptography

Traditional public key cryptographic methods provide access control to sensitive data by allowing the message sender to grant a single recipient permission to read the encrypted message. The Need2Know® system (N2K) improves upon these methods by providing role-based access control. N2K defines data access permissions similar to those of a multi-user file system, but N2K strictly enforces access through cryptographic standards. Since custom hardware can efficiently implement many cryptographic algorithms and can provide additional security, N2K stands to benefit greatly from a hardware implementation. To this end, the main N2K algorithm, the Key Protection Module (KPM), is being specified in VHDL. The design is being built and tested incrementally: this first phase implements the core control logic of the KPM without integrating its cryptographic sub-modules. Both RTL simulation and formal verification are used to test the design. This is the first N2K implementation in hardware, and it promises to provide an accelerated and secured alternative to the software-based system. A hardware implementation is a necessary step toward highly secure and flexible deployments of the N2K system

Modern methods of mixed-signal integrated circuit verification

Práce se zabývá metodami, které jsou vhodné pro verifikaci smíšených integrovaných obvodů. Důraz je přitom kladen na tzv. „Assertion-based“ verifikaci. Tato metoda je v praxi aplikovatelná pomocí jazyků PSL a SystemVerilog. Tyto jazyky jsou mezi sebou porovnány a samostatně otestovány, aby byl následně stanoven jejich potenciál a aby byly nalezeny jejich funkční hranice a omezení. Jeden z těchto jazyků bude následně začleněn do verifikačních postupů společnosti SCG Czech Design Center s. r. o., aby zde mohla být rozvinuta metoda ABV i v analogové a smíšené doméně.This work aims at methods, which are suitable for mixed-signal integrated circuit verification. The emphasis is on the Assertion-based verification. In practice there are two languages, which can be used for this method - PSL and SystemVerilog. These languages are compared between each other and individually tested to find their capabilities, functional limits and restrictions. One of them will be integrated into verification flow of SCG Czech Design Center s. r. o. company to develop ABV methodology in analog and mixed-signal domain.