Analysis of GF (2m) Multiplication Algorithm: Classic Method v/s Karatsuba-Ofman Multiplication Method

In recent years, finite field multiplication in GF(2m) has been widely used in various applications such as error correcting codes and cryptography. One of the motivations for fast and area efficient hardware solution for implementing the arithmetic operation of binary multiplication , in finite field GF (2m), comes from the fact, that they are the most time-consuming and frequently called operations in cryptography and other applications. So, the optimization of their hardware design is critical for overall performance of a system. Since a finite field multiplier is a crucial unit for overall performance of cryptographic systems, novel multiplier architectures, whose performances can be chosen freely, is necessary. In this paper, two Galois field multiplication algorithms (used in cryptography applications) are considered to analyze their performance with respect to parameters viz. area, power, delay, and the consequent Area×Time (AT) and Power×Delay characteristics. The objective of the analysis is to find out the most efficient GF(2m) multiplier algorithm among those considered

Implementacion de aritmetica de torres de campos finitos binarios de extension 2

The present work shows the basics of arithmetic of binary finite fields GF (2m), using the concept of extended towers of fields GF (22m), in this case with quadratic extension. Using field towers improve the computation of operations over finite fields, which is applied in the calculation of bilinear pairings, a main part of the identity- based cryptography; we present the basic concepts of arithmetic in GF (2m) and construction of operations addition, multiplication and multiplicative inverse in extended binary fields. Similarly presents the results of the implementation in a Xilinx FPGA device XV5LX110T, developed using VHDL language and tool ISE Design Suite System Edition 13.4En el presente trabajo se muestran los aspectos básicos de la aritmética de campos finitos binarios GF(2m) extendidos, usando el concepto de torres de campos GF(22m), en este caso con extensión 2 o cuadrática. El uso de torres de campos agiliza el cómputo de operaciones en los campos finitos, lo cual es aplicado en el cálculo de emparejamientos bilineales, parte fundamental de la criptografía basada en identidad. Se presentan los conceptos básicos de aritmética en GF(2m) y la construcción de las operaciones suma y multiplicación en campos binarios extendidos. De igual manera, se presentan los resultados de la implementación en un dispositivo FPGA XV5LX110T de Xilinx Inc., desarrollada usando lenguaje VHDL y la herramienta ISE Design Suite System Edition 13.4

Implementation of tower of finite field arithmetics in binary quadratic forms for fpga

En el presente trabajo se muestran los aspectos básicos de la aritmética de campos finitos binarios GF(2m), extendidos usando el concepto de torres de campos GF(22m), en este caso con extensión 2 o cuadrática. El uso de torres de campos agiliza el cómputo de operaciones en los campos finitos, lo cual es aplicado en el cálculo de emparejamientos bilineales, parte fundamental de la criptografía basada en identidad; se presentan los conceptos básicos de aritmética en GF(2m) y la construcción de las operaciones suma y multiplicación en campos binarios extendidos. De igual manera, se presentan los resultados de la implementación en un dispositivo FPGA XV5LX110T de Xilinx Inc., desarrollada usando lenguaje VHDL y la herramienta ISE Design Suite System Edition 14.4This work shows the basics of the arithmetic of binary finite fields GF (2m), using the concept of extended towers of fields GF (22m), in this case with quadratic extension. Using field towers improve the calculation of finite fields operations, which is applied in the calculation of bilinear pairings, a main part of identity-based cryptography. The basic concepts of arithmetic in GF (2m) are presented, as well as the construction of operations such as addition, multiplication, and multiplicative inverse in extended binary fields. Similarly, it presents the results of its implemen-tation in a Xilinx FPGA device XV5LX110T, which was developed using VHDL language and the ISE Design Suite System Edition 14.4 too

Методи та засоби підвищення ефективності реалізації обчислювальних операцій у скінченних полях

У дисертаційній роботі вирішено актуальну науково-прикладну задачу – підвищення продуктивності систем цифрової обробки даних та криптографічних перетворень, забезпечення завадостійкості зберігання і передачі даних за рахунок створення ефективних технічних засобів для виконання обчислень у скінченних полях шляхом структурно-логічної оптимізації архітектур апаратних засобів, що реалізують процеси виконання операцій у полях Галуа. Запропоновано метод виконання операцій над елементами поля GF(2m). Особливістю даного методу, на відміну від існуючих, є застосування табличного зберігання елементів поля у многочленному та степеневому їх поданні з можливістю розрідженого формування таблиці елементів поля, що зменшує витрати пам’яті для її зберігання. Розроблений метод забезпечує зростання швидкодії на 15% порівняно з існуючим методом. Запропоновано модифікацію методу піднесення до степеня елементів поля GF(p) з ковзним вікном, яка забезпечує приріст швидкодії на 7-9 %. Спроектовано на ПЛІС фірми Xilinx процесор Галуа, що орієнтований на виконання операцій у скінченних полях виду GF(p) та GF(2m). Запропоновано програмістську модель процесора Галуа, яка дозволяє розробляти програмне забезпечення довільної складності мовою Асемблера процесора Галуа.The thesis is devoted to the problem of increasing the efficiency of computations in finite fields. The proposed solution to this problem is to develop methods and means for performing operations on elements of finite fields GF(p) or GF(2m). The analysis of the current state of the development of methods of operations in finite fields is carried out and priority points are highlighted. It is best to classify them on the basis of the distinguished features. The classification of the methods of performing the most computational expensive operations (the calculation of the multiplicative inverse element and the exponentiation) in the finite fields was performed. It enables to conduct thorough research and form the directions of development for these methods. The method of high-speed implementation of additive and multiplicative operations on elements of GF(2m) and corresponding hardware structures for its implemen-tation are proposed. Additive operations include addition and subtraction. Multiplica-tive operations include multiplication, exponentiation, multiplicative inverse element calculation, and division. The research has shown that table storage of elements of the GF(2m) in their polynomial and power representation ensures the maximum speed and versatility of the arithmetic logic unit. With the use of long integer operands, the sparse formation of the table of field elements is proposed. It enables reducing the memory consumption for its storage in several times. The algorithms for converting power representa-tion into polynomial one and polynomial representation in power one with the use of a sparse table are constructed. The developed method provides a 15% increase in per-formance comparing with the existing method. Experimental researches were performed to determine the best sparse ratio of the elements table of the GF(2m). It has been discovered that for a value of m < 21, the best sparse ratio is equal to 8. For the exponentiation, it is desirable to increase the sparse ratio to 16. The algorithms for converting the power representation into polynomial one and polynomial representation into power one with the use of a sparse table are devel-oped. The modification of the method of exponentiation elements GF(p) with sliding window and the corresponding hardware structures for its implementation are pro-posed. The difference from the existing methods is that when forming a precomputation table, the exponents are prime numbers, and when analyzing the binary represen-tation of the exponent, blocks of bits forming a prime number are allocated. To achieve high performance, when constructing a precomputation table, it is recom-mended to use pre-calculated additive chains to minimize the number of multiplica-tion operations, which allows each of the following table items to be obtained in one or two modular multiplication operations. With the help of the developed computational model, it has been found out that the proposed modification of the exponentiation method of elements GF(p) with a sliding window provides an increase in speed by 7-9%. The modification of the ex-ponentiation method of elements GF(p) with a sliding window can be used in elliptic-curve cryptography to improve the time characteristics of the scalar multiplication on elliptic curve. The model of the computational process of execution of operations in finite fields is developed, which enables comparison of methods on the basis of given sets of input data and the execution of the optimal choice of parameters and forms of presentation of operands, which ensure an increase in speed for the implementation of computing operations on the FPGA. The research methodologies of new methods hardware implementation of calculations in Galois fields are developed on the basis of the proposed model. Simulation in the development environment of Xilinx ISE and using the Mentor Graphics Precision software showed that the developed hardware structures are characterized by minimal hardware complexity and high performance. A Verilog code generator for FPGA synthesis of a ROM element containing a sparse table of GF(2m) field elements in a polynomial and power representation is created which automatically generates a Verilog code for a given irreducible polyno-mial and a sparse ratio of the table. The architecture and the command system of the specialized Galois processor, focused on operations in finite fields, has been developed. The Galois processor can be used in a universal computing system as a coprocessor, complementing the com-mand system of the central processor unit, or as a special device based on the FPGA, which increases the efficiency of processing information in real time in comparison with the universal computing means. The architecture feature of the developed processor is that a user can change the arithmetic logic unit (ALU) to make the transition to the GF(p) or GF(2m) without changing the processor interface. The research of the developed Galois processor has been carried out, which showed that this processor provides an increase in the productivity of computing by 27% compared with the universal computing means. A program model of the Galois processor is constructed, which allows the user to create software of arbitrary complexity in Assembler of the Galois processor.В диссертационной работе решена актуальная научно-прикладная задача – повышение производительности систем цифровой обработки данных и крипто-графических преобразований, обеспечение помехоустойчивости хранения и передачи данных за счет создания эффективных технических средств для выполнения вычислений в конечных полях путем структурно-логической оптимизации архитектур аппаратных средств, реализующих процессы выполнения операций в полях Галуа. Предложен метод выполнения операций над элементами поля GF(2m). Особенностью данного метода, в отличие от существующих, является применение табличного хранения элементов поля в многочленном и степенном их представлении с возможностью разреженного формирования таблицы элементов поля, что уменьшает затраты памяти для ее хранения. Разработанный метод обеспечивает прирост производительности на 15% по сравнению с существующим методом. Предложена модификация метода возведения в степень элементов поля GF(p) со скользящим окном, обеспечивающая прирост быстродействия на 7-9%. Спроектирован на ПЛИС фирмы Xilinx процессор Галуа, ориентированный на выполнение операций в конечных полях вида GF(p) и GF(2m). Предложена программистская модель процессора Галуа, позволяющая разрабатывать программное обеспечение любой сложности на языке ассемблера процессора Галуа