Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them

Bio-inspired 0.35μm CMOS Time-to-Digital Converter with 29.3ps LSB

Time-to-digital converter (TDC) integrated circuit is introduced in this paper. It is based on chain of delay elements composing a regular scalable structure. The scheme is analogous to the sound direction sensitivity nerve system found in barn owl. The circuit occupies small silicon area, and its direct mapping from time to position-code makes conversion rates up to 500Msps possible. Specialty of the circuit is the structural and functional symmetry. Therefore the role of start and stop signals are interchangeable. In other words negative delay is acceptable: the circuit has no dead time problems. These are benefits of the biology model of the auditory scene representation in the bird's brain. The prototype chip is implemented in 0.35μm CMOS having less than 30ps single-shot resolution in the measurements.Hungarian National Research Foundation TS4085

CMOS array design automation techniques

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed

X-ray analog pixel array detector for single synchrotron bunch time-resolved imaging

Dynamic x-ray studies may reach temporal resolutions limited by only the x-ray pulse duration if the detector is fast enough to segregate synchrotron pulses. An analog integrating pixel array detector with in-pixel storage and temporal resolution of around 150 ns, sufficient to isolate pulses, is presented. Analog integration minimizes count-rate limitations and in-pixel storage captures successive pulses. Fundamental tests of noise and linearity as well as high-speed laser measurements are shown. The detector resolved individual bunch trains at the Cornell High Energy Synchrotron Source (CHESS) at levels of up to 3.7x10^3 x-rays/pixel/train. When applied to turn-by-turn x-ray beam characterization single-shot intensity measurements were made with a repeatability of 0.4% and horizontal oscillations of the positron cloud were detected. This device is appropriate for time-resolved Bragg spot single crystal experiments.Comment: 9 pages, 11 figure

Quantum dot-photonic crystal chips for quantum information processing

We have recently developed a technique for local, reversible tuning of individual quantum dots on a photonic crystal chip by up to 1.8nm, which overcomes the problem of large quantum dot inhomogeneous broadening - usually considered the main obstacle in employing such platform in practical quantum information processing systems. We have then used this technique to tune single quantum dots into strong coupling with a photonic crystal cavity, and observed strong coupling both in photoluminescence and in resonant light scattering from the system, as needed for several proposals for scalable quantum information networks and quantum computation

MEMS Technologies Enabling the Future Wafer Test Systems

As the form factor of microelectronic systems and chips are continuing to shrink, the demand for increased connectivity and functionality shows an unabated rising trend. This is driving the evolution of technologies that requires 3D approaches for the integration of devices and system design. The 3D technology allows higher packing densities as well as shorter chip-to-chip interconnects. Micro-bump technology with through-silicon vias (TSVs) and advances in flip chip technology enable the development and manufacturing of devices at bump pitch of 14 μm or less. Silicon carrier or interposer enabling 3D chip stacking between the chip and the carrier used in packaging may also offer probing solutions by providing a bonding platform or intermediate board for a substrate or a component probe card assembly. Standard vertical probing technologies use microfabrication technologies for probes, templates and substrate-ceramic packages. Fine pitches, below 50 μm bump pitch, pose enormous challenges and microelectromechanical system (MEMS) processes are finding applications in producing springs, probes, carrier or substrate structures. In this chapter, we explore the application of MEMS-based technologies on manufacturing of advanced probe cards for probing dies with various new pad or bump structures

Design of LCOS microdisplay backplanes for projection applications

De evolutie van licht emitterende diodes (LED) heeft ervoor gezorgd dat het op dit moment interessant wordt om deze componenten als lichtbron te gebruiken in projectiesystemen. LED’s hebben belangrijke voordelen vergeleken met klassieke booglampen. Ze zijn compact, ze hebben een veel grotere levensduur en ogenblikkelijke schakeltijden, ze werken op lage spanningen, etc. LED’s zijn smalbandig en kunnen een groterekleurenbereik realiseren. Ze hebben momenteel echter een beperkte helderheid. Naast de lichtbron is het type van de lichtklep ook bepalend voor de kwaliteit van een projectiesysteem. Er bestaan verschillende lichtkleptechnologieën waaronder die van de reflectieve LCOS-panelen. Deze lichtkleppen kunnen zeer hoge resoluties hebben en wordenvaak gebruikt in kwalitatieve, professionele projectiesystemen. LED’s zijn echter totaal verschillend van booglampen. Ze hebben een andere vorm, package, stralingspatroon, aansturing, fysische en thermische eigenschappen, etc. Hoewel er een twintigtal optische architecturen bekend zijn voor reflectieve beeldschermen (met een booglamp als lichtbron), zijn ze niet geschikt voor LED-projectoren en moeten nieuwe optische architecturen en een elektronische aansturing ontwikkeld worden. In dit doctoraat werd er hieromtrent onderzoek gedaan. Er werd uiteindelijk een driekleurenprojector (R, G, B) met een efficiënt LED-belichtingssysteem gebouwd met twee LCOS-lichtkleppen. Deze LEDprojector heeft superieure eigenschappen (zeer lange levensduur, beeldkwaliteit, etc.) en een matige lichtopbrengst

A Study on Controlling Power Supply Ramp-Up Time in SRAM PUFs

With growing connectivity in the modern era, the risk of encrypted data stored in hardware being exposed to third-party adversaries is higher than ever. The security of encrypted data depends on the secrecy of the stored key. Conventional methods of storing keys in Non-Volatile Memory have been shown to be susceptible to physical attacks. Physically Unclonable Functions provide a unique alternative to conventional key storage. SRAM PUFs utilize inherent process variation caused during manufacturing to derive secret keys from the power-up values of SRAM memory cells. This thesis analyzes the effect of supply ramp-up times on the reliability of SRAM PUFs. We use SPICE simulations as the platform to observe the effect of supply ramp times at the circuit level using carefully controlled supply voltages during power-up. We also measure the effect of supply ramp times on commercially available SRAM ICs by performing reliability and uniqueness measurements on two commercial SRAM models. Finally, a hardware implementation is proposed in a commercial 16nm FinFET technology to establish the design flow for taping out a custom SRAM IC with separated peripheral and core power supplies that would allow for experimental evaluation of sequenced power supplies on the SRAM PUF

Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability

Despite power boundaries, Moore's law is still present via scaling the number of cores, which keeps adding demands for more memory bandwidth (MBW) requested by these cores. To obtain higher MBW levels, it is fundamental to address memory controller (MC) scalability. However, MC scalability growth is limited by I/O pin counts scaling. To underline MC and pin scaling, a radio frequency(RF) I/O pad-scalable package-based (RFiop) memory organization is further investigated. In RFiop, a RF pad (RFpad) is defined as a quilt-packaging (QP) coplanar waveguide employed at RF ranges. An RFpad connects a rank to an RFMC which is formed by coupling MCs to RF transmitter/receivers. By using QP package to explore the architectural benefits of laying out ranks, RFiop replaces the traditional memory path with an RF-based one, while exploring the scalability of RFpads/RFMCs via RF signaling. When evaluating RFiop, our findings show that MBW/performance are enhanced by around 4.3x which can be viewed as a diminution in transaction queue occupancy/latency as well as using a reduced and scalable 4-8 RFpads per RFMC. RFiop architectural area benefits allow MBW/performance improvements of around 3.2x, while reducing interconnection energy up to 78%

A Detailed Analysis of Contemporary ARM and x86 Architectures

RISC vs. CISC wars raged in the 1980s when chip area and processor design complexity were the primary constraints and desktops and servers exclusively dominated the computing landscape. Today, energy and power are the primary design constraints and the computing landscape is significantly different: growth in tablets and smartphones running ARM (a RISC ISA) is surpassing that of desktops and laptops running x86 (a CISC ISA). Further, the traditionally low-power ARM ISA is entering the high-performance server market, while the traditionally high-performance x86 ISA is entering the mobile low-power device market. Thus, the question of whether ISA plays an intrinsic role in performance or energy efficiency is becoming important, and we seek to answer this question through a detailed measurement based study on real hardware running real applications. We analyze measurements on the ARM Cortex-A8 and Cortex-A9 and Intel Atom and Sandybridge i7 microprocessors over workloads spanning mobile, desktop, and server computing. Our methodical investigation demonstrates the role of ISA in modern microprocessors? performance and energy efficiency. We find that ARM and x86 processors are simply engineering design points optimized for different levels of performance, and there is nothing fundamentally more energy efficient in one ISA class or the other. The ISA being RISC or CISC seems irrelevant