MISSED: an environment for mixed-signal microsystem testing and diagnosis

A tight link between design and test data is proposed for speeding up test-pattern generation and diagnosis during mixed-signal prototype verification. Test requirements are already incorporated at the behavioral level and specified with increased detail at lower hierarchical levels. A strict distinction between generic routines and implementation data makes reuse of software possible. A testability-analysis tool and test and DFT libraries support the designer to guarantee testability. Hierarchical backtrace procedures in combination with an expert system and fault libraries assist the designer during mixed-signal chip debuggin

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Self-healing concepts involving fine-grained redundancy for electronic systems

The start of the digital revolution came through the metal-oxide-semiconductor field-effect transistor (MOSFET) in 1959 followed by massive integration onto a silicon die by means of constant down scaling of individual components. Digital systems for certain applications require fault-tolerance against faults caused by temporary or permanent influence. The most widely used technique is triple module redundancy (TMR) in conjunction with a majority voter, which is regarded as a passive fault mitigation strategy. Design by functional resilience has been applied to circuit structures for increased fault-tolerance and towards self-diagnostic triggered self-healing. The focus of this thesis is therefore to develop new design strategies for fault detection and mitigation within transistor, gate and cell design levels. The research described in this thesis makes three contributions. The first contribution is based on adding fine-grained transistor level redundancy to logic gates in order to accomplish stuck-at fault-tolerance. The objective is to realise maximum fault-masking for a logic gate with minimal added redundant transistors. In the case of non-maskable stuck-at faults, the gate structure generates an intrinsic indication signal that is suitable for autonomous self-healing functions. As a result, logic circuitry utilising this design is now able to differentiate between gate faults and faults occurring in inter-gate connections. This distinction between fault-types can then be used for triggering selective self-healing responses. The second contribution is a logic matrix element which applies the three core redundancy concepts of spatial- temporal- and data-redundancy. This logic structure is composed of quad-modular redundant structures and is capable of selective fault-masking and localisation depending of fault-type at the cell level, which is referred to as a spatiotemporal quadded logic cell (QLC) structure. This QLC structure has the capability of cellular self-healing. Through the combination of fault-tolerant and masking logic features the QLC is designed with a fault-behaviour that is equal to existing quadded logic designs using only 33.3% of the equivalent transistor resources. The inherent self-diagnosing feature of QLC is capable of identifying individual faulty cells and can trigger self-healing features. The final contribution is focused on the conversion of finite state machines (FSM) into memory to achieve better state transition timing, minimal memory utilisation and fault protection compared to common FSM designs. A novel implementation based on content-addressable type memory (CAM) is used to achieve this. The FSM is further enhanced by creating the design out of logic gates of the first contribution by achieving stuck-at fault resilience. Applying cross-data parity checking, the FSM becomes equipped with single bit fault detection and correction

An efficient logic fault diagnosis framework based on effect-cause approach

Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits, determining the source of failure in a defective circuit is becoming more and more challenging. In this research, we present an efficient effect-cause diagnosis framework for combinational VLSI circuits. The framework consists of three stages to obtain an accurate and reasonably precise diagnosis. First, an improved critical path tracing algorithm is proposed to identify an initial suspect list by backtracing from faulty primary outputs toward primary inputs. Compared to the traditional critical path tracing approach, our algorithm is faster and exact. Second, a novel probabilistic ranking model is applied to rank the suspects so that the most suspicious one will be ranked at or near the top. Several fast filtering methods are used to prune unrelated suspects. Finally, to refine the diagnosis, fault simulation is performed on the top suspect nets using several common fault models. The difference between the observed faulty behavior and the simulated behavior is used to rank each suspect. Experimental results on ISCAS85 benchmark circuits show that this diagnosis approach is efficient both in terms of memory space and CPU time and the diagnosis results are accurate and reasonably precise

Prognostics and Health Management of Electronics by Utilizing Environmental and Usage Loads

Prognostics and health management (PHM) is a method that permits the reliability of a system to be evaluated in its actual application conditions. Thus by determining the advent of failure, procedures can be developed to mitigate, manage and maintain the system. Since, electronic systems control most systems today and their reliability is usually critical for system reliability, PHM techniques are needed for electronics. To enable prognostics, a methodology was developed to extract load-parameters required for damage assessment from irregular time-load data. As a part of the methodology an algorithm that extracts cyclic range and means, ramp-rates, dwell-times, dwell-loads and correlation between load parameters was developed. The algorithm enables significant reduction of the time-load data without compromising features that are essential for damage estimation. The load-parameters are stored in bins with a-priori calculated (optimal) bin-width. The binned data is then used with Gaussian kernel function for density estimation of the load-parameter for use in damage assessment and prognostics. The method was shown to accurately extract the desired load-parameters and enable condensed storage of load histories, thus improving resource efficiency of the sensor nodes. An approach was developed to assess the impact of uncertainties in measurement, model-input, and damage-models on prognostics. The approach utilizes sensitivity analysis to identify the dominant input variables that influence the model-output, and uses the distribution of measured load-parameters and input variables in a Monte-Carlo simulation to provide a distribution of accumulated damage. Using regression analysis of the accumulated damage distributions, the remaining life is then predicted with confidence intervals. The proposed method was demonstrated using an experimental setup for predicting interconnect failures on electronic board subjected to field conditions. A failure precursor based approach was developed for remaining life prognostics by analyzing resistance data in conjunction with usage temperature loads. Using the data from the PHM experiment, a model was developed to estimate the resistance based on measured temperature values. The difference between actual and estimated resistance value in time-domain were analyzed to predict the onset and progress of interconnect degradation. Remaining life was predicted by trending several features including mean-peaks, kurtosis, and 95% cumulative-values of the resistance-drift distributions

Electronic Circuits Diagnosis Using Artificial Neural Networks

When we expect  about something that does not treat as it should be,  we are initiating the  process of diagnosis. Diagnosis is a commonly used activity in our everyday lives (Benjamins & Jansweijer, 1990). Complicated systems are always prone to faults or failures. In the simplest term, a fault is every change in a system that prevents it from operating in the proper manner. We define diagnosis as the task of identifying the cause and location of a fault manifested by some observed behaviour. Basically this is  two-stage process: first the fact that fault has occurred must be recognized – this is referred to as fault detection. That is, in general, achieved by testing. Secondly, the nature and location should be determined such that appropriate remedial action may be initiated