Simulation of FinFET Structures

The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications

Journal of Telecommunications and Information Technology, 2004, nr 1

kwartalni

Enhancing the Performance of Poly(3-Hexylthiophene) Based Organic Thin-Film Transistors Using an Interface Engineering Method

An original design and photolithographic fabrication process for poly(3-hexylthiophene-2, 5-diyl) (P3HT) based organic thin-film transistors (OTFTs) is presented. The structure of the transistors was based on the bottom gate bottom contact OTFT. The fabrication process was efficient, cost-effective, and relatively straightforward to implement. Current–voltage (I-V) measurements were performed to characterize the primary electronic properties of the transistors. The measured mobility of these transistors was significantly higher than most results reported in the literature for other similar bottom gate bottom contact P3HT OTFTs. The higher mobility is explained primarily by the effectiveness of the fabrication process in keeping the interfacial layers free from contamination, as well as the proper annealing of the P3HT. An interface engineering method is investigated to further enhance the performance of the OTFTs. Three interfacial materials were used for this purpose: graphene oxide (GO), poly(oligo (ethylene glycol) methyl ether methacrylate- glycidyl methacrylate- lauryl methacrylate) (P(OEGMA-GMA-LMA)) or POGL, and a composite of GO and P(OEGMA-GMA-LMA) or GO-POGL. The OTFTs with a GO interfacial layer were observed to have a higher drain current and field-effect mobility than the OTFTs with no interfacial layer. The enhanced drain current and mobility are associated with the particular structure of the P3HT layer on the dielectric surface and the reduction in the contact resistance between the GO-covered electrodes and the P3HT. The OTFTs with a POGL interfacial layer were observed to have a smaller threshold voltage than the OTFTs with no interfacial layer. The POGL OTFTs were also observed to have much more ideal drain current saturation characteristics with very small I-V curve slope. This is explained by the deep trap states on the POGL surface and the reduction of the contact resistance at the electrode/organic semiconductor interface. The OTFTs with a GO-POGL composite layer were observed to have a higher drain current and mobility, and a smaller threshold voltage than the OTFTs without an interfacial layer, which is the optimum case for these two device parameters. The higher drain current and field-effect mobility are attributed to the larger interconnecting grains of the P3HT that is deposited onto the GO-POGL surface and the smaller interfacial tension between the GO-POGL and the P3HT. The smaller threshold voltage is attributed to the deep trap states on the GO-POGL layer and the smaller contact resistance between the GO-POGL modified electrodes and the P3HT. Furthermore, experiments that could be performed to advance this research work and enhance the performance of the OTFTs even further are proposed

Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications

Silicon-on-Insulator (SOI) MOSFETs have been the primary precursor for the CMOS technology since last few decades offering superior device performance in terms of package density, speed, and reduced second order harmonics. Recent trends of investigation have stimulated the interest in Fully Depleted (FD) SOI MOSFET because of their remarkable scalability efficiency. However, some serious issues like short channel effects (SCEs) viz drain induced barrier lowering (DIBL), Vth roll-off, subthreshold slope (SS), and hot carrier effects (HCEs) are observed in nanoscale regime. Numerous advanced structures with various engineering concepts have been addressed to reduce the above mentioned SCEs in SOI platform. Among them strain engineering, high-k gate dielectric with metal gate technology (HKMG), and non-classical multigate technologies are most popular models for enhancement in carrier mobility, suppression of gate leakage current, and better immunization to SCEs. In this thesis, the performance of various emerging device designs are analyzed in nanoscale with 2-D modeling as well as through calibrated TCAD simulation. These attempts are made to reduce certain limitations of nanoscale design and to provide a significant contribution in terms of improved performances of the miniaturized devices. Various MOS parameters like gate work function (_m), channel length (L), channel thickness (tSi), and gate oxide thickness (tox) are optimized for both FD-SOI and Multiple gate technology. As the semiconductor industries migrate towards multigate technology for system-on-chip (SoC), system-in-package (SiP), and internet-of-things (IoT) applications, an appropriate examination of the advanced multiple gate MOFETs is required for the analog/RF application keeping reliability issue in mind. Various non-classical device structures like gate stack engineering and halo doping in the channel are extensively studied for analog/RF applications in double gate (DG) platform. A unique attempt has been made for detailed analysis of the state-of-the-art 3-D FinFET on dependency of process variability. The 3-D architecture is branched as Planar or Trigate or FinFET according to the aspect ratio (WFin=HFin). The evaluation of zero temperature coefficient (ZTC) or temperature inflection point (TCP) is one of the key investigation of the thesis for optimal device operation and reliability. The sensitivity of DG-MOSFET and FinFET performances have been addressed towards a wide range of temperature variations, and the ZTC points are identified for both the architectures. From the presented outcomes of this work, some ideas have also been left for the researchers for design of optimum and reliable device architectures to meet the requirements of high performance (HP) and/or low standby power (LSTP) applications

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors

Metal-oxide semiconductor field-effect transistor (MOSFET) scaling throughout the years has enabled us to pack million of MOS transistors on a single chip to keep in pace with Moore’s Law. After forty years of advances in integrated circuit (IC) technology, the scaling of silicon (Si) MOSFET has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. The latest technological advancement has led to a low power, high-density and high-speed generation of processor. Nevertheless, the scaling of the Si MOSFET below 22 nm may soon meet its’ fundamental physical limitations. This threshold makes the possible use of novel devices and structures such as carbon nanotube field-effect transistors (CNTFETs) and graphene nanoribbon field-effect transistors (GNRFETs) for future nanoelectronics. The investigation explores the potential of these amazing carbon structures that exceed MOSFET capabilities in term of speed, scalability and power consumption. The research findings demonstrate the potential integration of carbon based technology into existing ICs. In particular, a simulation program with integrated circuit emphasis (SPICE) model for CNTFET and GNRFET in digital logic applications is presented. The device performance of these circuit models and their design layout are then compared to 45 nm and 90 nm MOSFET for benchmarking. It is revealed through the investigation that CNT and GNR channels can overcome the limitations imposed by Si channel length scaling and associated short channel effects while consuming smaller channel area at higher current density

Development of CCD and EM-CCD Technology for High Resolution X-Ray Spectrometry

This thesis discusses the development of Charge-Couple Device (CCD) and Electron Multiplying CCD (EM-CCD) technology for high resolution X-ray spectroscopy. Of particular interest is the spectral resolution performance of the devices alongside the optimisation of the quantum efficiency through the use of back-illuminated CCDs, thin filter technology and improved passivation techniques. The early chapters (1 through 5) focus on the background and theory that is required to understand the purpose of the work in this thesis and how semiconductors can be used as the detector of high resolution X-ray spectrometers. Chapter 6 focuses on the soft X-ray performance of three different types of conventional CCD using the PTB beamline at BESSY II. The results show that there is degradation in spectral resolution in all three devices below 500 eV due to incomplete charge collection and X-ray peak asymmetry. The Hamamatsu device is shown to degrade faster than the CCD30-11 variants and this is attributed to the thickness of the active silicon (>50 μm) in the device and also its thicker dead-layer (~75 nm) which is found by evaluating the device's soft X-ray QE). The charge loss at the back-surface generation/recombination centres is also investigated and is found to be higher in the Hamamatsu device, again due to its thicker dead-layer. Chapter 7 is an investigation of the Modified Fano Factor which aims to describe the spectral resolution degradation that is expected when an EM-CCD is used to directly detect soft X-rays. The factor is predicted analytically, modelled and then verified experimentally allowing EM-CCD performance over the soft X-ray range to be predicted with high levels of confidence. Chapter 8 is a detailed look into work completed for the phase 0 study of the off plane X-ray grating spectrometer on the International X-ray Observatory. The work includes a detailed contamination study, effective area analysis, the pointing knowledge requirement and the use of filters to minimise optical background